Commit Graph

1031420 Commits

Author SHA1 Message Date
Lee Shawn C
5ebd50d394 drm/i915/dsi: refine send MIPI DCS command sequence
According to chapter "Sending Commands to the Panel" in bspec #29738
and #49188. If driver try to send DCS long pakcet, we have to program
TX payload register at first. And configure TX header HW register later.
DSC long packet would not be sent properly if we don't follow this
sequence.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210908115607.9633-3-shawn.c.lee@intel.com
2021-09-08 19:34:39 +05:30
Lee Shawn C
43315f86a3 drm/i915/dsi: wait for header and payload credit available
Driver should wait for free header or payload buffer in FIFO.
It would be good to wait a while for HW to release credit before
give it up to write to HW. Without sending initailize command
sets completely. It would caused MIPI display can't light up properly.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210908115607.9633-2-shawn.c.lee@intel.com
2021-09-08 19:34:38 +05:30
José Roberto de Souza
0f3692b5e4 drm/i915/display: Prepare DRRS for frontbuffer rendering drop
Frontbuffer rendering will be dropped for modern platforms but
before that we to prepare DRRS for it.

intel_drrs_flush and intel_drrs_invalidate will not be called
for platforms that will not support frontbuffer rendering so DRRS
needs another way to be notified about to page flips so it can change
between high and low refresh rates as needed.

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210903221036.34770-3-jose.souza@intel.com
2021-09-07 15:39:43 -07:00
José Roberto de Souza
6bd58b70af drm/i915/display: Share code between intel_drrs_flush and intel_drrs_invalidate
Both functions are pretty much equal, with minor changes that can be
handled by a single parameter.

v3:
- not scheduling work from invalidate operations

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210903221036.34770-2-jose.souza@intel.com
2021-09-07 15:39:43 -07:00
José Roberto de Souza
c7c4dfb6fe drm/i915/display: Some code improvements and code style fixes for DRRS
It started as a code style fix for the lines above 100 col but it
turned out to simplifications to intel_drrs_set_state().
Now it receives the desired refresh rate type, high or low.

v3:
- Fixed the mode refesh rate debug message

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210903221036.34770-1-jose.souza@intel.com
2021-09-07 15:39:42 -07:00
Jani Nikula
5a449e5864 drm/i915/bios: get rid of vbt ddi_port_info
We can finally remove the extra caching in ddi_port_info. Good riddance.

v2: Rebased

Cc: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f56e864d10bb3cbe616288450d92b56325d1df12.1630512523.git.jani.nikula@intel.com
2021-09-07 10:29:28 +03:00
Jani Nikula
dab8477b03 drm/i915/bios: use ddc pin directly from child data
Avoid extra caching of the data. This is slightly more subtle than one
would think. For one thing, we explicitly ignore 0 value in child device
ddc pin; this is specified as N/A and does not warrant a warning. For
another, we start looking for ddc pin collisions in sanitize using
unmapped pin numbering.

v2: Check !devdata in intel_bios_alternate_ddc_pin()

Cc: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e1dbf7cbdd2191439e760ab9098242dcec5fbb2e.1630512523.git.jani.nikula@intel.com
2021-09-07 10:29:21 +03:00
Jani Nikula
9e1dbc1a84 drm/i915/bios: move ddc pin mapping code next to ddc pin sanitize
Move code around to avoid a forward declaration in the future.

Cc: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/8c5f723e0b2d8ffd6f47068edf710947b45843be.1630512523.git.jani.nikula@intel.com
2021-09-07 10:29:18 +03:00
Jani Nikula
11182986b4 drm/i915/bios: use alternate aux channel directly from child data
Avoid extra caching of the data.

v2: Check for !info->devdata in intel_bios_port_aux_ch() (Ankit)

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b1b9f0032b353c3279b4546d6acdb696fe0b6136.1630512523.git.jani.nikula@intel.com
2021-09-07 10:29:14 +03:00
Jani Nikula
72337aac00 drm/i915/bios: use dp max link rate directly from child data
Avoid extra caching of the data.

Cc: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/5593ce81f6670dc33cf18fa284f8237c875ef404.1630512523.git.jani.nikula@intel.com
2021-09-07 10:29:11 +03:00
Jani Nikula
6ba6998145 drm/i915/bios: use max tmds clock directly from child data
Avoid extra caching of the data.

Cc: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/451082780a8befb2b27919439c901a2159ce173f.1630512523.git.jani.nikula@intel.com
2021-09-07 10:29:06 +03:00
Jani Nikula
a9a56e7628 drm/i915/bios: use hdmi level shift directly from child data
Avoid extra caching of the data.

Cc: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ef22e40b01eab571ff0dc2bfffabb906d0151fb4.1630512523.git.jani.nikula@intel.com
2021-09-07 10:28:48 +03:00
Animesh Manna
555ae26d51 drm/i915/dp: fix for ADL_P/S dp/edp max source rates
Added HBR3 support for ADL_P and ADL_S platform.

Bspec: 53597, 53720, 49185, 55409

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210901160402.24816-6-animesh.manna@intel.com
2021-09-02 15:42:51 +03:00
Jani Nikula
bc41f059a0 drm/i915/dp: fix DG1 and RKL max source rates
Combo phy is limited to 5.4 GHz on low-voltage SKUs, but both eDP and DP
can do 8.1 GHz on combo phy.

Bspec: 49182, 49205, 49202

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210901160402.24816-5-animesh.manna@intel.com
2021-09-02 15:42:50 +03:00
Animesh Manna
8ee8167771 drm/i915/dp: fix EHL/JSL max source rates calculation
Only higher voltage sku can support HBR3 so a condition
check added in max source rate calculation for ehl/jsl.

Bspec: 32247, 20598

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210901160402.24816-4-animesh.manna@intel.com
2021-09-02 15:42:50 +03:00
Jani Nikula
533140cb51 drm/i915/dp: fix TGL and ICL max source rates
Combo phy is limited to 5.4 GHz on low-voltage SKUs. Combo phy DP is
limited to 5.4 GHz, while combo phy eDP can do 8.1 GHz.

Bspec: 20584, 20598, 49180, 49201

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210901160402.24816-3-animesh.manna@intel.com
2021-09-02 15:42:49 +03:00
Matt Atwood
6fd5a7c92e drm/i915/dp: Fix eDP max rate for display 11+
intel_dp_set_source_rates() calls intel_dp_is_edp(), which is unsafe to
use before intel_encoder->type is set. This causes incorrect max source
rate to be used for display 11+. On EHL and JSL, HBR3 is used instead of
HBR2, and on the other affected platforms, HBR2 is used instead of HBR3.

Move intel_dp_set_source_rates() to after intel_encoder->type is
set. Add comment to intel_dp_is_edp() describing unsafe usages. Cleanup
intel_dp_init_connector() while at it.

Note: The same change was originally added as commit 680c45c767
("drm/i915/dp: Correctly advertise HBR3 for GEN11+"), but later reverted
due to issues in CI in commit d391301960 ("Revert "drm/i915/dp:
Correctly advertise HBR3 for GEN11+"").

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210901160402.24816-2-animesh.manna@intel.com
2021-09-02 15:42:48 +03:00
Jani Nikula
344c327830 drm/i915/debugfs: clean up LPSP capable
Clean up the LPSP capability printout. No functional changes.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/097390f12da8de57c9d52ad675309d0422dec8fb.1630327990.git.jani.nikula@intel.com
2021-09-02 14:12:10 +03:00
Jani Nikula
3a5f9281cf drm/i915/debugfs: clean up LPSP status
Clean up the LPSP status printout. No functional changes.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c7c2db4e1434ed9a3545f2561a03dc593db5e674.1630327990.git.jani.nikula@intel.com
2021-09-02 14:11:59 +03:00
Jani Nikula
802fd9613e drm/i915/dp: fix DG2 max source rate check
Accidentally dropped the else in a rebase fail, causing the DG2 max rate
to be overwritten later in the if ladder.

Fixes: e752d1f9c1 ("drm/i915/dg2: add DG2 UHBR source rates")
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210901112815.16498-1-jani.nikula@intel.com
2021-09-02 13:26:55 +03:00
Vandita Kulkarni
19ba2e8e27 drm/i915/dsi/xelpd: Enable mipi dsi support.
Enable MIPI DSI support on ADL-P platform.
The esc clock changes, WA changes are taken care
in the previous patches.
As per the Bspec the seq remains to be same as TGL.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210826054811.10572-3-vandita.kulkarni@intel.com
2021-09-01 13:07:41 +05:30
Vandita Kulkarni
f87c46c431 drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband
Wa_16012360555 SW will have to program the "LP to HS Wakeup Guardband"
field to account for the repeaters on the HS Request/Ready PPI signaling
between the Display engine and the DPHY.

v2: Fix build issue.
v3: Align to new naming (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210826054811.10572-2-vandita.kulkarni@intel.com
2021-09-01 13:07:41 +05:30
Vandita Kulkarni
f7a8f9afe5 drm/i915/display: Update small joiner ram size
Xelpd supports larger small joiner ram.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210805101937.14664-1-vandita.kulkarni@intel.com
2021-09-01 13:06:27 +05:30
José Roberto de Souza
3a3dd5342f drm/i915/display: Renaming DRRS functions to intel_drrs_*()
We had a mix of intel_edp_drrs_*(), intel_dp_drrs_*() and
intel_dp_set_drrs_state(), so properly renaming all functions to
keep the same pattern.

While at it, also dropping intel_dp_set_drrs_state from the
documentation as it is a static function.

v3:
- dropping documentation style comment in static function
(intel_drrs_set_state)

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210827174253.51122-3-jose.souza@intel.com
2021-08-30 12:39:59 -07:00
José Roberto de Souza
a1b63119ee drm/i915/display: Move DRRS code its own file
intel_dp.c is a 5k lines monster, so moving DRRS out of it to reduce
some lines from it.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210827174253.51122-2-jose.souza@intel.com
2021-08-30 12:39:57 -07:00
José Roberto de Souza
ad26451a79 drm/i915/display: Drop PSR support from HSW and BDW
At this point is sure that HSW and BDW will never have PSR enabled by
default, so here dropping it from device info and cleaning up code.

v2:
- enable psr support for display 9

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210827174253.51122-1-jose.souza@intel.com
2021-08-30 12:39:56 -07:00
Animesh Manna
45cbbe50cc drm/i915/dg2: UHBR tables added for pll programming
UHBR modes has higher link rate and added new values for programming
mpll of SNPS phy. No change in sequence, only the pll parameters
are different for UHBR modes.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210827103843.527-1-jani.nikula@intel.com
2021-08-30 13:24:44 +03:00
Jani Nikula
fa3217c494 drm/i915: remove unused i915->active_pipes
Apparently the last reader of i915->active_pipes was removed with commit
ef79d62b5c ("drm/i915: Encapsulate dbuf state handling harder"), and
now it's only ever written to. Remove it completely.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210826141830.889-1-jani.nikula@intel.com
2021-08-30 12:20:59 +03:00
Jani Nikula
9716846039 drm/i915/fdi: convert BUG()'s to MISSING_CASE()
These shouldn't happen, but in the off chance they do, we'll want a
warning rather than panic.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b86132ac63f43f79e51eb63f948beccba85bf449.1629906431.git.jani.nikula@intel.com
2021-08-27 11:43:57 +03:00
Jani Nikula
e2cf6afcda drm/i915/fdi: move fdi mphy reset and programming to intel_fdi.c
This fairly detailed stuff that really has no place in
intel_display.c. Combine the calls into one to avoid exposing both.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b0037775480380e5d73d0b112da478d6f0ea30fe.1629906431.git.jani.nikula@intel.com
2021-08-27 11:43:54 +03:00
Jani Nikula
12b2c3016d drm/i915/fdi: move more FDI stuff to FDI link train hooks
Accept slight duplication in the fdi link train hooks in exchange for
simplification in ilk_pch_enable(). This lets us make
ivb_update_fdi_bc_bifurcation() static again, now in intel_fdi.c.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7984e670c6bb092d213d90f838d526d594d4a690.1629906431.git.jani.nikula@intel.com
2021-08-27 11:43:51 +03:00
Jani Nikula
f18362cd28 drm/i915/fdi: move fdi bc bifurcation functions to intel_fdi.c
Move FDI related functions to intel_fdi.c. Don't bother with renaming as
we'll make the functions static shortly.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/fd8afe4876f0b0762a9c69e01762a8dba31349e5.1629906431.git.jani.nikula@intel.com
2021-08-27 11:43:47 +03:00
Jani Nikula
0ce2982582 drm/i915/fdi: move intel_update_fdi_pll_freq to intel_fdi.c
Move FDI related functions to intel_fdi.c. Rename to have intel_fdi
prefix while at it.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/da1609dfce4623f8ec86254aea6c2c8679b6a37f.1629906431.git.jani.nikula@intel.com
2021-08-27 11:43:36 +03:00
Rodrigo Vivi
13d696743c Merge tag 'drm-misc-intel-oob-hotplug-v1' of git://git.kernel.org/pub/scm/linux/kernel/git/hansg/linux into drm-intel-next
Topic branch for drm-misc / drm-intel for OOB hotplug support for Type-C connectors

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

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# gpg: Signature made Fri 20 Aug 2021 01:29:15 PM EDT
# gpg:                using RSA key BAF03B5D2718411A5E9E177E92EC4779440327DC
# gpg:                issuer "hdegoede@redhat.com"
# gpg: Can't check signature: No public key
From: Hans de Goede <hdegoede@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/34f13e21-9b1a-5f54-7e03-9705a6b51428@redhat.com
2021-08-26 07:37:25 -04:00
Jani Nikula
3a8e7fd66e drm/i915/snps: constify struct intel_mpllb_state arrays harder
The tables should be const arrays of const pointers, not just arrays of
const pointers.

Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210825145811.4227-1-jani.nikula@intel.com
2021-08-26 12:06:34 +03:00
Jani Nikula
4b93f49d08 drm/i915/panel: mass rename functions to have intel_panel_ prefix
Follow the usual naming conventions. Also pull HAS_GMCH() check to
intel_panel_fitting(). No functional changes.

Cc: Lyude Paul <lyude@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/9ff6e42e377bdb0c9349f50d9ea79671059633c7.1629888677.git.jani.nikula@intel.com
2021-08-26 10:40:41 +03:00
Jani Nikula
c0a52f8bd7 drm/i915/backlight: mass rename functions to have intel_backlight_ prefix
Follow the usual naming conventions. As a drive-by cleanup, also pass
intel_connector instead of drm_connector to intel_backlight_setup(). No
functional changes.

Cc: Lyude Paul <lyude@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ea1c22370210abdd4f5547af73c71b902061ea50.1629888677.git.jani.nikula@intel.com
2021-08-26 10:40:41 +03:00
Jani Nikula
6cc42fbeb1 drm/i915/backlight: extract backlight code to a separate file
In a long overdue refactoring, split out backlight code to new
intel_backlight.[ch]. Simple code movement, leave renames for follow-up
work. No functional changes.

Cc: Lyude Paul <lyude@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/97d310848f03061473b9b2328e2c5c4dcf263cfa.1629888677.git.jani.nikula@intel.com
2021-08-26 10:40:41 +03:00
Matt Roper
d3252e1a3b drm/i915/dg2: Memory latency values from pcode must be doubled
The memory latency values returned by pcode on DG2 are in units of "2
usec" rather than 1 usec on all other platforms.  I.e., we need to
double the value returned by pcode to obtain the true latency value.

The bspec wording here was a bit ambiguous as to whether it wanted us to
multiply or divide the pcode value by two, but we confirmed offline with
the hardware team that we need to double the value the pcode gives us;
this change is intended to support a larger range of potential latency
values.

Bspec: 49326
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Harish Chegondi <harish.chegondi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210820225710.401136-1-matthew.d.roper@intel.com
2021-08-25 15:05:20 -07:00
Ville Syrjälä
76a04cd9af drm/i915: Nuke intel_prepare_shared_dpll()
intel_prepare_shared_dpll() is now useless, so get rid of it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-14-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-08-25 17:14:31 +03:00
Ville Syrjälä
0bae0872f8 drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable()
Move the FP divider programming into ibx_pch_dpll_enable(). No reason
that I can see why these would have to be programmed this early.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-13-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-08-25 17:14:19 +03:00
Ville Syrjälä
62d66b2183 drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll()
Can't think of a good reason why we'd need to program the FP
dividers so early. Let's just do it when programming the rest
of the DPLL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-12-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-08-25 17:14:08 +03:00
Ville Syrjälä
7b43cd70b5 drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as well
Use ilk_needs_fb_cb_tune() for reduced_clock instead of hand rolling
it. Also ilk_needs_fb_cb_tune() can just use the precomputed M value
instead of calculating it again.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-11-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-08-25 17:13:53 +03:00
Ville Syrjälä
a338847abc drm/i915: Call {vlv,chv}_prepare_pll() from {vlv,chv}_enable_pll()
We always call the vlv/chv prepare_pll() just before enable_pll().
Move the calls into the enable_pll() funcs. We can also
consolidate the DPLL_VCO_ENABLE checks while at it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-10-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-08-25 17:11:34 +03:00
Ville Syrjälä
98b27e7989 drm/i915: Program DPLL P1 dividers consistently
On g4x and pch the DPLL has two P1 dividers (for refresh rate
switching). Program the FPx1 P1 divider consistently to the reduced
clock P1 divider if available, otherwise just program it to the
same value as the FPx0 P1 divider.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-08-25 17:11:10 +03:00
Ville Syrjälä
510e890e82 drm/i915: Remove the 'reg' local variable
Get rid of the local 'reg' variable for the DPLL control register
in i9xx_enable_pll(). We have other registers in there too so this
is just making things more confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-08-25 17:09:33 +03:00
Ville Syrjälä
8a3b3df397 drm/i915: Clean up variable names in old dpll functions
s/pipe_config/crtc_state/ in the DPLL code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-08-25 17:08:53 +03:00
Ville Syrjälä
6205372b4b drm/i915: Clean dpll calling convention
Stop passing both the crtc and its state to the DPLL functions.
The state alone is enough.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-08-25 17:08:40 +03:00
Ville Syrjälä
24951b5813 drm/i915: Constify struct dpll all over
Lots of places don't need to modify the DPLL params, so make
them const.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-08-25 17:08:02 +03:00
Ville Syrjälä
b294425e90 drm/i915: Extract ilk_update_pll_dividers()
Make the PCH dpll code match the gmch code by splitting
the FP register handling out from ilk_compute_dpll().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-08-25 17:05:58 +03:00