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Author SHA1 Message Date
Konrad Dybcio
574af54562 arm64: dts: qcom: sm6350: Add PRNG node 
Add a node for the PRNG to enable hw-accelerated pseudo-random number
generation.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-12-konrad.dybcio@somainline.org
 2021-09-27 17:21:29 -05:00
Konrad Dybcio
001eaf9514 arm64: dts: qcom: sm6350: Add SPMI bus 
Add a node for SPMI to allow for communication with on-board PMICs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-11-konrad.dybcio@somainline.org
 2021-09-27 17:21:29 -05:00
Konrad Dybcio
8fe2e0d9db arm64: dts: qcom: sm6350: Add AOSS_QMP 
Add a node for AOSS_QMP in preparation for remote processor enablement.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-10-konrad.dybcio@somainline.org
 2021-09-27 17:21:29 -05:00
Konrad Dybcio
25e0ae6848 arm64: dts: qcom: sm6350: Add TSENS nodes 
Add nodes required for TSENS block using the common qcom,tsens-v2 binding.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-9-konrad.dybcio@somainline.org
 2021-09-27 17:21:29 -05:00
Konrad Dybcio
3cc415413f arm64: dts: qcom: sm6350: Add cpufreq-hw support 
Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable
CPU clock scaling.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-8-konrad.dybcio@somainline.org
 2021-09-27 17:21:28 -05:00
Konrad Dybcio
23737b9557 arm64: dts: qcom: sm6350: Add USB1 nodes 
Add nodes required for USB1 to function. SM6350 (thankfully) resuses SDM845 and
SC7180 IP, so no additional code porting is required.

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
[bjorn: Renamed dwc3 node "usb"]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-7-konrad.dybcio@somainline.org
 2021-09-27 17:21:15 -05:00
Konrad Dybcio
538f4bcd51 arm64: dts: qcom: sm6350: Add TLMM block node 
Add TLMM pinctrl node to enable referencing the SoC pins in other nodes.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-6-konrad.dybcio@somainline.org
 2021-09-27 17:11:13 -05:00
Konrad Dybcio
30de1108df arm64: dts: qcom: sm6350: Add GCC node 
Add and configure GCC node to allow for referencing GCC-controlled clocks
in other nodes.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-5-konrad.dybcio@somainline.org
 2021-09-27 17:11:13 -05:00
Konrad Dybcio
985e02e7c0 arm64: dts: qcom: sm6350: Add RPMHCC node 
Add RPMHCC node to allow for referencing RPMH-controlled clocks in other
nodes.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-4-konrad.dybcio@somainline.org
 2021-09-27 17:11:13 -05:00
Konrad Dybcio
ced2f0d75e arm64: dts: qcom: sm6350: Add LLCC node 
Add a node for LLCC with SM6350-specific compatible.

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-3-konrad.dybcio@somainline.org
 2021-09-27 17:11:13 -05:00
Konrad Dybcio
5f82b9cda6 arm64: dts: qcom: Add SM6350 device tree 
Add a base DT for SM6350 SoC

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-2-konrad.dybcio@somainline.org
 2021-09-27 17:11:13 -05:00
Konrad Dybcio
55d0feb3ab dt-bindings: arm: cpus: Add Kryo 560 CPUs 
Document Kryo 560 CPUs found in Qualcomm Snapdragon 690 (SM6350).

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-1-konrad.dybcio@somainline.org
 2021-09-27 17:11:13 -05:00
Sibi Sankar
6b7cb2d237 arm64: dts: qcom: sm8350: Use QMP property to control load state 
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8350 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-11-git-send-email-sibis@codeaurora.org
 2021-09-27 14:58:38 -05:00
Sibi Sankar
b74ee2d71b arm64: dts: qcom: sm8250: Use QMP property to control load state 
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8250 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-10-git-send-email-sibis@codeaurora.org
 2021-09-27 14:58:37 -05:00
Sibi Sankar
d9d327f6a3 arm64: dts: qcom: sm8150: Use QMP property to control load state 
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8150 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-9-git-send-email-sibis@codeaurora.org
 2021-09-27 14:58:36 -05:00
Sibi Sankar
db8e45a81b arm64: dts: qcom: sdm845: Use QMP property to control load state 
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SDM845 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-8-git-send-email-sibis@codeaurora.org
 2021-09-27 14:58:35 -05:00
Sibi Sankar
6b3207dfeb arm64: dts: qcom: sc7280: Use QMP property to control load state 
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SC7280 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-7-git-send-email-sibis@codeaurora.org
 2021-09-27 14:58:34 -05:00
Sibi Sankar
1357804562 arm64: dts: qcom: sc7180: Use QMP property to control load state 
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SC7180 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-6-git-send-email-sibis@codeaurora.org
 2021-09-27 14:58:32 -05:00
Douglas Anderson
be4c096e6b arm64: dts: qcom: sc7180: Base homestar's power coefficients in reality 
The commit 82ea7d411d ("arm64: dts: qcom: sc7180: Base dynamic CPU
power coefficients in reality") and the commit be0416a3f9 ("arm64:
dts: qcom: Add sc7180-trogdor-homestar") passed each other in the
tubes that make up the Internet. Despite the fact the patches didn't
cause a merge conflict, they need to account for each other. Do that.

Fixes: 82ea7d411d ("arm64: dts: qcom: sc7180: Base dynamic CPU power coefficients in reality")
Fixes: be0416a3f9 ("arm64: dts: qcom: Add sc7180-trogdor-homestar")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923081352.1.I2a2ee0ac428a63927324d65022929565aa7d8361@changeid
 2021-09-24 18:28:32 -05:00
AngeloGioacchino Del Regno
6cadaa14f2 arm64: dts: qcom: msm8998-xperia: Add audio clock and its pin 
All smartphones of this platform are equipped with a WCD9335 audio
codec, getting its MCLK from PM8998 gpio13: add this clock to DT.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210909123733.367248-7-angelogioacchino.delregno@somainline.org
 2021-09-24 18:25:23 -05:00
AngeloGioacchino Del Regno
a5fde05939 arm64: dts: qcom: msm8998-xperia: Add camera regulators 
All of the machines of the Sony Yoshino platform are equipped with
two cameras, sharing the same regulators configuration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210909123733.367248-6-angelogioacchino.delregno@somainline.org
 2021-09-24 18:25:23 -05:00
AngeloGioacchino Del Regno
67372ee2c0 arm64: dts: qcom: msm8998-xperia: Configure display boost regulators 
Add configuration for the LAB and IBB regulators (in boost mode):
this platform has smartphones with three different display sizes,
hence different displays requiring different voltage.

The common configuration parameters have been put in the common
device-tree, while specific voltage specs and soft-start-us are
variant specific, so they have been put into the machine specific
dts file.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210909123733.367248-5-angelogioacchino.delregno@somainline.org
 2021-09-24 18:25:23 -05:00
AngeloGioacchino Del Regno
4de9700d03 arm64: dts: qcom: msm8998-xperia: Add support for gpio vibrator 
All smartphones in the Sony Yoshino platforms have got a simple
vibrator hooked to a GPIO: add support for that and add its own
pin configuration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210909123733.367248-4-angelogioacchino.delregno@somainline.org
 2021-09-24 18:25:23 -05:00
AngeloGioacchino Del Regno
58ba4efabc arm64: dts: qcom: msm8998-xperia: Add support for wcn3990 Bluetooth 
This platform uses the WCN3990 Bluetooth chip, reachable on UART-3.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210909123733.367248-3-angelogioacchino.delregno@somainline.org
 2021-09-24 18:25:23 -05:00
AngeloGioacchino Del Regno
ebe0932e4f arm64: dts: qcom: msm8998-xperia: Add RMI4 touchscreen support 
All of the devices in the Sony Yoshino platform are using a Synaptics
RMI4-compatible touch IC with identical pins and supplies: enable the
I2C-5 bus and add the rmi4-i2c node along with the required pin
configurations.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210909123733.367248-2-angelogioacchino.delregno@somainline.org
 2021-09-24 18:25:22 -05:00
AngeloGioacchino Del Regno
390883af89 arm64: dts: qcom: msm8998: Introduce support for Sony Yoshino platform 
This commit introduces support for the Sony Yoshino platform, using
the MSM8998 SoC, including:
- Sony Xperia XZ1 (codename Poplar),
- Sony Xperia XZ1 Compact (codename Lilac),
- Sony Xperia XZ Premium (codename Maple).

All of the three aforementioned smartphones are sharing a 99%
equal board configuration, with very small differences between
each other, which is the reason for the introduction of a common
msm8998-sony-xperia-yoshino DT.

This base configuration includes regulators and project-wide pin
configurations and it's made to boot to a serial console.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210909123733.367248-1-angelogioacchino.delregno@somainline.org
 2021-09-24 18:25:12 -05:00
Shawn Guo
36730a8f5f arm64: dts: qcom: pm660: Add reboot mode support 
It turns out that the pm660 PON is a GEN2 device.  Update the compatible
to "qcom,pm8998-pon" and add reboot mode support, so that devices can be
rebooted into bootloader and recovery mode.  Tested on Xiaomi Redmi Note
7 phone.

While at it, drop the unnecessary newline between 'compatible' and 'reg'
property.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210824021918.17271-1-shawn.guo@linaro.org
 2021-09-24 17:56:33 -05:00
Rajesh Patil
5f65408d9b arm64: dts: qcom: sc7280: Add aliases for I2C and SPI 
Add aliases for i2c and spi for sc7280 soc.

Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1632399378-12229-9-git-send-email-rajpat@codeaurora.org
 2021-09-24 17:40:20 -05:00
Roja Rani Yarubandi
4e8e7648ae arm64: dts: qcom: sc7280: Add QUPv3 wrapper_1 nodes 
Add QUPv3 wrapper_1 DT nodes for SC7280 SoC.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1632399378-12229-8-git-send-email-rajpat@codeaurora.org
 2021-09-24 17:40:20 -05:00
Rajesh Patil
e3bc6fec5a arm64: dts: qcom: sc7280: Configure uart7 to support bluetooth on sc7280-idp 
Add bluetooth uart pin configuration for sc7280-idp.

Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1632399378-12229-7-git-send-email-rajpat@codeaurora.org
 2021-09-24 17:40:20 -05:00
Roja Rani Yarubandi
38cd93f413 arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node 
Uart5 is treated as dedicated debug uart.Change the
compatible as "qcom,geni-uart" in SoC DT to make it generic
and later update it as "qcom,geni-debug-uart" in sc7280-idp
Add interconnects and power-domains. Split the pinctrl
functions and correct the gpio pins.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1632399378-12229-6-git-send-email-rajpat@codeaurora.org
 2021-09-24 17:40:20 -05:00
Roja Rani Yarubandi
bf6f37a308 arm64: dts: qcom: sc7280: Add QUPv3 wrapper_0 nodes 
Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1632399378-12229-5-git-send-email-rajpat@codeaurora.org
 2021-09-24 17:40:20 -05:00
Rajesh Patil
df0174b13d arm64: dts: qcom: sc7280: Configure SPI-NOR FLASH for sc7280-idp 
Add spi-nor flash node and pinctrl configurations for the SC7280 IDP.

Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1632399378-12229-4-git-send-email-rajpat@codeaurora.org
 2021-09-24 17:40:20 -05:00
Roja Rani Yarubandi
7720ea001b arm64: dts: qcom: sc7280: Add QSPI node 
Add QSPI DT node and qspi_opp_table for SC7280 SoC.

Move qspi_opp_table to / because SPI nodes assume
any child node is a spi device and so we can't put the
table underneath the spi controller.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1632399378-12229-3-git-send-email-rajpat@codeaurora.org
 2021-09-24 17:40:20 -05:00
Fabio Estevam
07b2fb6046 arm64: dts: qcom: sm6125: Remove leading zeroes 
dtc complains about the leading zeroes:

arch/arm64/boot/dts/qcom/sm6125.dtsi:497.19-503.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f121000: unit name should not have leading 0s
arch/arm64/boot/dts/qcom/sm6125.dtsi:505.19-510.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f123000: unit name should not have leading 0s
arch/arm64/boot/dts/qcom/sm6125.dtsi:512.19-517.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f124000: unit name should not have leading 0

Remove them.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210922195208.1734936-1-festevam@gmail.com
 2021-09-23 21:22:33 -05:00
Shaik Sajida Bhanu
752432e40e arm64: dts: qcom: sc7180: Use maximum drive strength values for eMMC 
The current drive strength values are not sufficient on non discrete
boards and this leads to CRC errors during switching to HS400 enhanced
strobe mode.

Hardware simulation results on non discrete boards shows up that use the
maximum drive strength values for data and command lines could helps
in avoiding these CRC errors.

So, update data and command line drive strength values to maximum.

Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1629132650-26277-1-git-send-email-sbhanu@codeaurora.org
 2021-09-23 15:26:38 -05:00
Sujit Kautkar
0c38d6b6a6 arm64: dts: qcom: sc7180-trogdor: Enable IPA on LTE only SKUs 
Enable the IPA node for LTE and skip for wifi-only SKUs

Signed-off-by: Sujit Kautkar <sujitka@chromium.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210920113220.v1.1.I904da9664f294fcf222f6f378d37eaadd72ca92e@changeid
 2021-09-21 18:24:23 -05:00
Stephan Gerhold
f633d5f74e arm64: dts: qcom: msm8916: Add "qcom,msm8916-sdhci" compatible 
According to Documentation/devicetree/bindings/mmc/sdhci-msm.txt
a SoC specific compatible should be used in addition to the IP version
compatible, but for some reason it was never added for MSM8916.

Add the "qcom,msm8916-sdhci" compatible additionally to make the
device tree match the documented bindings.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210921152120.6710-3-stephan@gerhold.net
 2021-09-21 18:24:23 -05:00
Stephan Gerhold
7a62bfebc8 arm64: dts: qcom: msm8916: Add unit name for /soc node 
This fixes the following warning when building with W=1:
Warning (unit_address_vs_reg): /soc: node has a reg or ranges property,
but no unit name

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210921152120.6710-1-stephan@gerhold.net
 2021-09-21 18:24:23 -05:00
Stephen Boyd
33b89923d0 arm64: dts: qcom: sc7280: Use GIC_SPI for intc cells 
Let's use the GIC_SPI macro instead of a plain 0 here to match other
uses of the primary interrupt controller on sc7280.

Suggested-by: Matthias Kaehlcke <mka@chromium.org>
Cc: Alex Elder <elder@linaro.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210811181904.779316-1-swboyd@chromium.org
 2021-09-21 18:24:23 -05:00
Manaf Meethalavalappu Pallikunhi
b39f266c19 arm64: dts: qcom: sc7280: Add gpu thermal zone cooling support 
Add cooling-cells property and the cooling maps for the gpu thermal
zones to support GPU thermal cooling.

Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1628691835-36958-2-git-send-email-akhilpo@codeaurora.org
 2021-09-21 18:24:23 -05:00
Akhil P Oommen
96c471970b arm64: dts: qcom: sc7280: Add gpu support 
Add the necessary dt nodes for gpu support in sc7280.

Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1628691835-36958-1-git-send-email-akhilpo@codeaurora.org
 2021-09-21 18:24:23 -05:00
Taniya Das
c8efde9f6b arm64: dts: qcom: sc7280: Add clock controller ID headers 
Add the GPUCC, DISPCC and VIDEOCC clock headers which were dropped
earlier.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1628642571-25383-1-git-send-email-tdas@codeaurora.org
 2021-09-21 18:24:23 -05:00
satya priya
bd7dd79ca3 arm64: dts: qcom: sc7280: Add volume up support for sc7280-idp 
Add pm7325 PMIC gpio support for vol+ on sc7280-idp.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631877040-26587-1-git-send-email-skakit@codeaurora.org
 2021-09-21 18:24:23 -05:00
Dmitry Baryshkov
7a5fca9550 arm64: dts: qcom: qrb5165-rb5: enabled pwrkey and resin nodes 
Enable powerkey and resin nodes to let the board handle POWER and
Volume- keys properly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210916151341.1797512-3-dmitry.baryshkov@linaro.org
 2021-09-21 18:24:23 -05:00
Dmitry Baryshkov
aea101ba75 arm64: dts: qcom: pm8150: specify reboot mode magics 
Specify recovery and bootloader magic values to be programmed by the
qcom-pon driver. This allows the bootloader to handle
reboot-to-bootloader functionality.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210916151341.1797512-2-dmitry.baryshkov@linaro.org
 2021-09-21 18:24:23 -05:00
Dmitry Baryshkov
d68170ae44 arm64: dts: qcom: pm8150: use qcom,pm8998-pon binding 
Change pm8150 to use the qcom,pm8998-pon compatible string for the pon
in order to pass reboot mode properly.

Fixes: 5101f22a5c ("arm64: dts: qcom: pm8150: Add base dts file")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210916151341.1797512-1-dmitry.baryshkov@linaro.org
 2021-09-21 18:24:23 -05:00
Kathiravan T
20bb9e3dd2 arm64: dts: qcom: ipq6018: add usb3 DT description 
Based on downstream codeaurora code.

Tested (USB2 only) on IPQ6010 based hardware.

Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
[bjorn: Changed dwc3 node name to usb, per binding]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/ebc2d340d566fa2d43127e253d5b8b134a87a78e.1630389452.git.baruch@tkos.co.il
 2021-09-21 18:24:23 -05:00
Shawn Guo
bbef0142f5 arm64: dts: qcom: Update BAM DMA node name per DT schema 
Follow dma-controller.yaml schema to use `dma-controller` as node name
of BAM DMA devices.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210831052325.21229-1-shawn.guo@linaro.org
 2021-09-21 18:24:23 -05:00
Douglas Anderson
65751ebea0 arm64: dts: qcom: sc7280: Move the SD CD GPIO pin out of the dtsi file 
There's nothing magical about GPIO91 and boards could use different
GPIOs for card detect. Move the pin out of the dtsi file and to the
only existing board file.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210830080621.1.Ia15d97bc4a81f2916290e23a8fde9cbc66186159@changeid
 2021-09-21 18:24:23 -05:00