mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-04-26 13:22:44 -04:00
Code Issues Packages Projects Releases Wiki Activity
900,432 Commits 1 Branch 927 Tags
53a2cc5cc36fd97728e1b418dbfa8f70bf23391a
Commit Graph

900432 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Stephen Boyd
53a2cc5cc3 Merge branches 'clk-ti', 'clk-ingenic', 'clk-typo', 'clk-at91', 'clk-mmp2' and 'clk-arm-icst' into clk-next 
- EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs
 - Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs
 - Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers

* clk-ti:
  clk: keystone: Add new driver to handle syscon based clocks
  dt-bindings: clock: Add binding documentation for TI EHRPWM TBCLK

* clk-ingenic:
  clk: ingenic/TCU: Fix round_rate returning error
  clk: ingenic/jz4770: Exit with error if CGU init failed
  clk: JZ4780: Add function for enable the second core.
  clk: Ingenic: Add support for TCU of X1000.

* clk-typo:
  clk: Fix trivia typo in comment exlusive => exclusive

* clk-at91:
  clk: at91: add at91rm9200 pmc driver
  clk: at91: add at91sam9n12 pmc driver
  clk: at91: add sama5d3 pmc driver
  clk: at91: add at91sam9g45 pmc driver
  clk: at91: usb: introduce num_parents in driver's structure
  clk: at91: usb: use proper usbs_mask
  clk: at91: sam9x60: fix usb clock parents
  clk: at91: usb: continue if clk_hw_round_rate() return zero
  clk: at91: sam9x60: Don't use audio PLL

* clk-mmp2:
  clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks
  clk: mmp2: Add clock for fifth SD HCI on MMP3
  dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3
  clk: mmp2: Add clocks for the thermal sensors
  dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors
  clk: mmp2: add the GPU clocks
  dt-bindings: marvell,mmp2: Add clock ids for the GPU clocks
  clk: mmp2: Add PLLs that are available on MMP3
  dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs
  clk: mmp2: Check for MMP3
  dt-bindings: clock: Add MMP3 compatible string
  clk: mmp2: Stop pretending PLL outputs are constant
  clk: mmp2: Add support for PLL clock sources
  dt-bindings: clock: Convert marvell,mmp2-clock to json-schema
  clk: mmp2: Constify some strings
  clk: mmp2: Remove a unused prototype

* clk-arm-icst:
  MAINTAINERS: dt: update reference for arm-integrator.txt
  clk: versatile: Add device tree probing for IM-PD1 clocks
  clk: versatile: Export icst_clk_setup()
  dt-bindings: clock: Create YAML schema for ICST clocks
 2020-04-03 15:09:55 -07:00
Stephen Boyd
2d11e9a1fd Merge branches 'clk-phase-errors', 'clk-amlogic', 'clk-renesas' and 'clk-allwinner' into clk-next 
- Don't show clk phase when it is invalid

* clk-phase-errors:
  clk: rockchip: fix mmc get phase
  clk: Fix phase init check
  clk: Bail out when calculating phase fails during clk registration
  clk: Move rate and accuracy recalc to mostly consumer APIs
  clk: Use 'parent' to shorten lines in __clk_core_init()
  clk: Don't cache errors from clk_ops::get_phase()

* clk-amlogic:
  clk: meson: meson8b: set audio output clock hierarchy
  clk: meson: g12a: add support for the SPICC SCLK Source clocks
  dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs
  clk: meson: gxbb: set audio output clock hierarchy
  clk: meson: gxbb: add the gxl internal dac gate
  dt-bindings: clk: meson: add the gxl internal dac gate

* clk-renesas:
  dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema
  clk: renesas: rcar-usb2-clock-sel: Add reset_control
  clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties
  clk: renesas: Remove use of ARCH_R8A7795
  clk: renesas: r8a77965: Add RPC clocks
  clk: renesas: r8a7796: Add RPC clocks
  clk: renesas: r8a7795: Add RPC clocks
  clk: renesas: rcar-gen3: Add CCREE clocks

* clk-allwinner:
  clk: sunxi-ng: sun8i-de2: Sort structures
  clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
  clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
  clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
  clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
  clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
  clk: sunxi-ng: sun8i-de2: Split out H5 definitions
  clk: sunxi-ng: a64: Export MBUS clock
 2020-04-03 15:09:32 -07:00
Stephen Boyd
ea0a1fb716 Merge branches 'clk-samsung', 'clk-formatting', 'clk-si5341' and 'clk-socfpga' into clk-next 
* clk-samsung:
  clk: samsung: Remove redundant check in samsung_cmu_register_one

* clk-formatting:
  clk: Fix continuation of of_clk_detect_critical()

* clk-si5341:
  clk, clk-si5341: Support multiple input ports

* clk-socfpga:
  clk: socfpga: stratix10: simplify parameter passing
  clk: stratix10: use do_div() for 64-bit calculation
 2020-04-03 15:09:22 -07:00
Mauro Carvalho Chehab
7928f4f6a2 MAINTAINERS: dt: update reference for arm-integrator.txt 
This file was renamed. Update references accordingly.

Fixes: 78c7d8f96b ("dt-bindings: clock: Create YAML schema for ICST clocks")

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lkml.kernel.org/r/491d2928a47f59da3636bc63103a5f63fec72b1a.1584966325.git.mchehab+huawei@kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-24 19:02:26 -07:00
Lubomir Rintel
de17be999c clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks 
They were reversed because I read the datasheet upside down.
Actually there is no datasheet, but I ended up understanding the
comments in Open Firmware driver wrong.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-18-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:41 -07:00
Lubomir Rintel
54198276ba clk: mmp2: Add clock for fifth SD HCI on MMP3 
There's one extra SDHCI on MMP3, used by the internal SD card on OLPC
XO-4. Add a clock for it.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-17-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:40 -07:00
Lubomir Rintel
c2ca122a0a dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3 
There's one extra SDHCI on MMP3, used by the internal SD card on OLPC
XO-4. Add a clock for it.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-16-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:40 -07:00
Lubomir Rintel
82d59c382c clk: mmp2: Add clocks for the thermal sensors 
The register definitions gotten from OLPC Open Firmware.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-15-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:40 -07:00
Lubomir Rintel
41a8632049 dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors 
There seems to be a single thermal sensor block on MMP2 and a couple
more on MMP3. Add definitions for their respective clocks.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-14-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:40 -07:00
Lubomir Rintel
bfa851b60c clk: mmp2: add the GPU clocks 
MMP2 has a single GC860 core while MMP3 has a GC2000 and a GC300.
On both platforms there's an AXI bus interface clock that's common for
all GPUs and each GPU core has a separate clock.

Meaning of the relevant APMU_GPU bits were gotten from James Cameron's
message and [1], the OLPC OS kernel source [2] and Marvell's MMP3 tree.

[1] http://lists.laptop.org/pipermail/devel/2019-April/039053.html
[2] http://dev.laptop.org/git/olpc-kernel/commit/arch/arm/mach-mmp/mmp2.c?h=arm-3.0-wip&id=8ce9f6122

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-13-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:40 -07:00
Lubomir Rintel
e3142226fe dt-bindings: marvell,mmp2: Add clock ids for the GPU clocks 
MMP2 has a single GC860 core while MMP3 has a GC2000 and a GC300.
On both platforms there's an AXI bus interface clock that's common for
all GPUs and each GPU core has a separate clock.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-12-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:40 -07:00
Lubomir Rintel
a70812b188 clk: mmp2: Add PLLs that are available on MMP3 
There are more PLLs on MMP3 and are configured slightly differently.
Tested on a MMP3-based Dell Wyse 3020 machine.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-10-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:32 -07:00
Lubomir Rintel
4d6da655d1 dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs 
MMP3 variant provides some more clocks. Add respective IDs.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200309194254.29009-9-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:32 -07:00
Lubomir Rintel
391bbbd2b2 clk: mmp2: Check for MMP3 
The MMP3's are similar enough to MMP2, but there are differencies, such
are more clocks available on the newer model. We want to tell which
platform are we on.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-8-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:32 -07:00
Lubomir Rintel
b90e0eb304 dt-bindings: clock: Add MMP3 compatible string 
This binding describes the PMUs that are found on MMP3 as well. Add the
compatible strings and adjust the description.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200309194254.29009-7-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:31 -07:00
Lubomir Rintel
ea56ad6026 clk: mmp2: Stop pretending PLL outputs are constant 
The hardcoded values for PLL1 and PLL2 are wrong. PLL1 is slightly
off -- it defaults to 797.33 MHz, not 800 MHz. PLL2 is disabled by default,
but also configurable.

Tested on a MMP2-based OLPC XO-1.75 laptop, with PLL1=797.33 and various
values of PLL2 set via set-pll2-520mhz, set-pll2-910mhz and
set-pll2-988mhz Open Firmware words.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-6-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:31 -07:00
Lubomir Rintel
5d34d0b32d clk: mmp2: Add support for PLL clock sources 
The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are
constant, but in fact they are configurable.

Add logic for obtaining the actual clock rates on MMP2 as well as MMP3.
There is no documentation for either SoC, but the "systemsetting" drivers
from Marvell GPL code dump provide some clue as far as MPMU registers on
MMP2 [1] and MMP3 [2] go.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c
[2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c

A separate commit will adjust the clk-of-mmp2 driver.

Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC
XO-1.75 laptop.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-5-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:31 -07:00
Lubomir Rintel
7de0b8b8b0 dt-bindings: clock: Convert marvell,mmp2-clock to json-schema 
Convert the fixed-factor-clock binding to DT schema format using
json-schema.

While at that, fix a couple of small errors: make the file base name
match the compatible string, add an example and document the reg-names
property.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200309194254.29009-4-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:31 -07:00
Lubomir Rintel
cb8dbfe831 clk: mmp2: Constify some strings 
All the parent clock names for the muxes are constant. Add const.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-3-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:30 -07:00
Lubomir Rintel
b3296386c5 clk: mmp2: Remove a unused prototype 
There is no mmp_clk_register_pll2() routine.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-2-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:19:30 -07:00
Alexandre Belloni
02ff48e4d7 clk: at91: add at91rm9200 pmc driver 
Add a driver for the PMC clocks of the at91rm9200.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lkml.kernel.org/r/20200214145934.53648-1-alexandre.belloni@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 18:18:58 -07:00
Linus Walleij
84655b762a clk: versatile: Add device tree probing for IM-PD1 clocks 
As we want to move these clocks over to probe from the device
tree we add a device tree probing path.

The old platform data path will be deleted once we have the
device tree overall code in place.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lkml.kernel.org/r/20200219103326.81120-3-linus.walleij@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 17:55:31 -07:00
Linus Walleij
eb9d6428a7 clk: versatile: Export icst_clk_setup() 
Export this clock setup method so we can register the
IM-PD1 clocks with common code in the next step.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lkml.kernel.org/r/20200219103326.81120-2-linus.walleij@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 17:55:31 -07:00
Linus Walleij
78c7d8f96b dt-bindings: clock: Create YAML schema for ICST clocks 
The ICST clocks used in the ARM Integrator, Versatile and
RealView platforms are updated to use YAML schema, and two
new ICST clocks used by the Integrator IM-PD1 logical module
are added in the process.

Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lkml.kernel.org/r/20200219103326.81120-1-linus.walleij@linaro.org
[sboyd@kernel.org: Fix some typos]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 17:55:21 -07:00
Andy Shevchenko
a37a5a9d71 clk: Fix trivia typo in comment exlusive => exclusive 
Fix trivia typo in comment exlusive => exclusive.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lkml.kernel.org/r/20200310135507.87959-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 17:12:48 -07:00
Paul Cercueil
edcc42945d clk: ingenic/TCU: Fix round_rate returning error 
When requesting a rate superior to the parent's rate, it would return
-EINVAL instead of simply returning the parent's rate like it should.

Fixes: 4f89e4b8f1 ("clk: ingenic: Add driver for the TCU clocks")
Cc: stable@vger.kernel.org
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20200213161952.37460-2-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 17:08:40 -07:00
Paul Cercueil
c067b46d73 clk: ingenic/jz4770: Exit with error if CGU init failed 
Exit jz4770_cgu_init() if the 'cgu' pointer we get is NULL, since the
pointer is passed as argument to functions later on.

Fixes: 7a01c19007 ("clk: Add Ingenic jz4770 CGU driver")
Cc: stable@vger.kernel.org
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reported-by: kbuild test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lkml.kernel.org/r/20200213161952.37460-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 17:08:40 -07:00
Vignesh Raghavendra
1aa0817e43 clk: keystone: Add new driver to handle syscon based clocks 
On TI's AM654/J721e SoCs, certain clocks can be gated/ungated by setting
a single bit in SoC's System Control Module registers. Sometime more
than one clock control can be in the same register.

Add a driver to support such clocks using syscon framework. Driver
currently supports controlling EHRPWM's TimeBase clock(TBCLK) for AM654
SoC.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lkml.kernel.org/r/20200227053529.16479-3-vigneshr@ti.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 17:07:21 -07:00
Vignesh Raghavendra
cf891c6be1 dt-bindings: clock: Add binding documentation for TI EHRPWM TBCLK 
Add DT bindings for TI EHRPWM's TimeBase clock (TBCLK) on TI's AM654 SoC.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lkml.kernel.org/r/20200227053529.16479-2-vigneshr@ti.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 17:05:48 -07:00
周琰杰 (Zhou Yanjie)
6673db4f3f clk: JZ4780: Add function for enable the second core. 
Add "jz4780_core1_enable()" for enable the second core of JZ4780,
prepare for later commits.

Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Link: https://lkml.kernel.org/r/1582215889-113034-3-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 17:02:03 -07:00
周琰杰 (Zhou Yanjie)
dc6a81c338 clk: Ingenic: Add support for TCU of X1000. 
X1000 has a different TCU, since X1000 OST has been independent of TCU.
This patch is add TCU support of X1000, and prepare for later OST driver.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lkml.kernel.org/r/1584457893-40418-3-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-20 17:01:38 -07:00
Stephen Boyd
8ca1f3c06f Merge tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner 
Pull Allwinner clk driver updates from Chen-Yu Tsai:

Changes consist mainly of cleanups for the display engine clock driver,
correcting clocks that don't exist. Also, the MBUS clock on the A64 is
exported for the device tree to consume.

* tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: sun8i-de2: Sort structures
  clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
  clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
  clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
  clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
  clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
  clk: sunxi-ng: sun8i-de2: Split out H5 definitions
  clk: sunxi-ng: a64: Export MBUS clock
 2020-03-16 11:22:39 -07:00
Stephen Boyd
f58272b6f6 Merge tag 'clk-renesas-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas 
Pull more Renesas clk driver updates from Geert Uytterhoeven:

  - Improved clock/reset handling for the R-Car USB2 Clock Selector
  - Conversion to json-schema of the Renesas CPG/MSSR DT bindings

* tag 'clk-renesas-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema
  clk: renesas: rcar-usb2-clock-sel: Add reset_control
  clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties
 2020-03-16 11:15:10 -07:00
Geert Uytterhoeven
eeb40fda05 dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema 
Convert the Renesas Clock Pulse Generator / Module Standby and Software
Reset Device Tree binding documentation to json-schema.

Note that #reset-cells was incorrecty marked a required property for
RZ/A2 before.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200303094848.23670-1-geert+renesas@glider.be
 2020-03-11 09:02:26 +01:00
Yoshihiro Shimoda
1ab4f43927 clk: renesas: rcar-usb2-clock-sel: Add reset_control 
This hardware needs to deassert resets of both host and peripheral.
So, this patch adds reset control.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1583304137-28482-5-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-03-09 09:29:58 +01:00
Yoshihiro Shimoda
80cf67dd01 clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management 
This hardware needs to enable clocks of both host and peripheral.
So, this patch adds multiple clocks management.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1583304137-28482-4-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-03-09 09:29:56 +01:00
Yoshihiro Shimoda
f70ae8ecf9 dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties 
This patch adds missing required properties of power-domains and resets.
Fortunately, no one has this device node for now, so that we don't
need to think of backward compatibility.

Fixes: 311accb645 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1583304137-28482-3-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-03-09 09:29:38 +01:00
Yoshihiro Shimoda
fc51da4c15 dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties 
Since the hardware requires to enable both USB 2.0 host and peripheral
functional clock, this patch fixes the documentation.
Fortunately, no one has this device node for now, so that we don't
need to think of backward compatibility.

Fixes: 311accb645 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1583304137-28482-2-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-03-09 09:29:38 +01:00
Stephen Boyd
dfbfee8702 Merge tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 
Pull Amlogic clk driver updates from Jerome Brunet:

 - Update audio clock gate hierarchy for meson8 and gxbb
 - Update g12a spicc clock sources

* tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: set audio output clock hierarchy
  clk: meson: g12a: add support for the SPICC SCLK Source clocks
  dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs
  clk: meson: gxbb: set audio output clock hierarchy
  clk: meson: gxbb: add the gxl internal dac gate
  dt-bindings: clk: meson: add the gxl internal dac gate
 2020-03-06 13:11:42 -08:00
Stephen Boyd
23b6bc70c1 Merge tag 'clk-renesas-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas 
Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add Crypto clocks on R-Car M3-W/W+, M3-N, E3, and D3
  - Add RPC (QSPI/HyperFLASH) clocks on R-Car H3, M3-W/W+, and M3-N

* tag 'clk-renesas-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: Remove use of ARCH_R8A7795
  clk: renesas: r8a77965: Add RPC clocks
  clk: renesas: r8a7796: Add RPC clocks
  clk: renesas: r8a7795: Add RPC clocks
  clk: renesas: rcar-gen3: Add CCREE clocks
 2020-03-06 12:07:19 -08:00
Jerome Brunet
d894992502 clk: rockchip: fix mmc get phase 
If the mmc clock has no rate, it can be assumed to be constant.
In such case, there is no measurable phase shift. Just return 0
in this case instead of returning an error.

Fixes: 2760878662 ("clk: Bail out when calculating phase fails during clk registration")
Tested-by: Markus Reichl <m.reichl@fivetechno.de>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20200303192956.64410-1-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-03-06 12:06:01 -08:00
Maxime Ripard
c3944ec8c6 clk: Fix phase init check 
Commit 2760878662 ("clk: Bail out when calculating phase fails during
clk registration") introduced a check on error values at the time the
clock is registered to bail out when such an error occurs. However, it
doesn't check whether the returned value is positive which will happen
if the driver returns a non-zero phase. Since a phase is usually a
non-zero positive number this ends up returning something that isn't 0
to the caller of __clk_core_init(), making most clks fail to register
if they implement a phase clk op and return anything besides 0 for the
phase.

Fix this by returning the error if phase is less than zero or just
return zero if the phase is a positive number.

Fixes: 2760878662 ("clk: Bail out when calculating phase fails during clk registration")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lkml.kernel.org/r/20200225134248.919889-1-maxime@cerno.tech
Reported-by: "kernelci.org bot" <bot@kernelci.org>
[sboyd@kernel.org: Reword commit text to provide clarity]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-02-28 10:57:03 -08:00
Geert Uytterhoeven
068e7f8523 clk: renesas: Remove use of ARCH_R8A7795 
CONFIG_ARCH_R8A7795 was split in CONFIG_ARCH_R8A77950 and
CONFIG_ARCH_R8A77951 in commit b925adfceb ("soc: renesas: Add
ARCH_R8A7795[01] for existing R-Car H3"), so its users can be removed.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200218112525.5834-1-geert+renesas@glider.be
 2020-02-21 14:01:54 +01:00
Martin Blumenstingl
71202c4124 clk: meson: meson8b: set audio output clock hierarchy 
The aiu devices peripheral clocks needs the aiu and aiu_glue clocks to
operate. Reflect this hierarchy in the clock tree.

Fixes: e31a1900c1 ("meson: clk: Add support for clock gates")
Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2020-02-21 11:44:41 +01:00
Neil Armstrong
a18c8e0b76 clk: meson: g12a: add support for the SPICC SCLK Source clocks 
This adds the clocks used for the Amlogic G12A and compatible SoCs SPICC
controller to provide a more complete range of frequencies instead of the
SPICC internal divider over Xtal.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2020-02-19 18:41:27 +01:00
Jerome Brunet
51a0c29b22 Merge branch 'v5.7/dt' into v5.7/drivers 2020-02-19 18:40:45 +01:00
Neil Armstrong
42be7c41a5 dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs 
Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2020-02-19 18:40:00 +01:00
Jerome Brunet
83b89a75de clk: meson: gxbb: set audio output clock hierarchy 
The aiu devices peripheral clocks needs the aiu and aiu_glue clocks to
operate. Reflect this hierarchy in the gxbb clock tree.

Fixes: 738f66d321 ("clk: gxbb: add AmLogic GXBB clk controller driver")
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2020-02-13 17:26:51 +01:00
Jerome Brunet
73c7ddd8ee clk: meson: gxbb: add the gxl internal dac gate 
Add the ACODEC clock gate to the gxl clk controller driver

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2020-02-13 17:26:04 +01:00
Jerome Brunet
306e59cc32 dt-bindings: clk: meson: add the gxl internal dac gate 
Add the gxl ACODEC clock id to the gxbb clock controller bindings

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2020-02-13 17:19:22 +01:00