A recent cleanup of soc_dai_link_sanity_check() is responsible for
generating lots of confusing errors before returning -EPROBE_DEFER:
acp5x_mach acp5x_mach.0: ASoC: Component acp5x_i2s_dma.0 not found for link acp5x-8821-play
[...]
acp5x_mach acp5x_mach.0: ASoC: Component spi-VLV1776:00 not found for link acp5x-CS35L41-Stereo
[...]
acp5x_mach acp5x_mach.0: ASoC: Component spi-VLV1776:01 not found for link acp5x-CS35L41-Stereo
Switch back to the initial behaviour of logging those messages on
KERN_DEBUG level instead of KERN_ERR.
While at it, use the correct form of the verb in 'component_not_find'
label.
Fixes: 0e66a2c694 ("ASoC: soc-core.c: cleanup soc_dai_link_sanity_check()")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com
Link: https://lore.kernel.org/r/20230824193837.369761-1-cristian.ciocaltea@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org
Current audio-graph-card functions definition are like below
(A)' static int graph_get_dais_count();
(B) int audio_graph_parse_of(...)
{
...
(A) ret = graph_get_dais_count();
...
}
(A) static int graph_get_dais_count(...)
{
...
}
(C)
We don't need to have (A)' definition if audio_graph_parse_of() (B) was
defined at (C). This patch moves (B) to (C).
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87r0ntmc3c.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org
clang warns (or errors with CONFIG_WERROR=y):
sound/soc/codecs/cs42l43.c:1371:2: error: variable 'ret' is used uninitialized whenever switch default is taken [-Werror,-Wsometimes-uninitialized]
1371 | default:
| ^~~~~~~
sound/soc/codecs/cs42l43.c:1377:9: note: uninitialized use occurs here
1377 | return ret;
| ^~~
sound/soc/codecs/cs42l43.c:1349:9: note: initialize the variable 'ret' to silence this warning
1349 | int ret;
| ^
| = 0
1 error generated.
Initialize ret to 0 in the default case, as there was nothing to do for
other event types.
Closes: https://github.com/ClangBuiltLinux/linux/issues/1922
Fixes: fc918cbe87 ("ASoC: cs42l43: Add support for the cs42l43")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20230823-cs42l43_pll_ev-init-ret-v1-1-5836f1ad5dad@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge series from Xingyu Wu <xingyu.wu@starfivetech.com>:
This patch series adds I2S support for the StarFive JH7110 RISC-V
SoC based on Designware I2S controller. There has three I2S channels
(RX/TX0/TX1) on the JH7110 SoC, one of which is for record(RX) and
two for playback(TX).
The first patch adds support for the StarFive JH7110 SoC in the
Designware I2S bindings.
The second patch adds the ops to get data from platform bus in the
I2S driver.
The third patch adds support for the StarFive JH7110 SoC in
the Designware I2S driver.
The fourth patch fixes the name of I2STX1 pinmux.
The last patch adds device node of I2S RX/TX0/TX1 in JH7110 dts.
This patch series is based on Linux-next(20230818) which is merge
clock, syscon and dma nodes for the StarFive JH7110 SoC.
The series has been tested and works normally on the VisionFive 2
board by plugging an audio expansion board.
Merge series from Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>:
Renesas Sound has ADG for clock control. Basically it needs
accurately divisible external input clock. But sometimes
sometimes it doesn't have to be accurate for some reason.
We can use ADG clk_i for such case. It came from CPG as
very high rate clock, but is not accurately divisible for
48kHz/44.1kHz rate, but enough for approximate rate.
This patch set support such use case.
Add StarFive JH7110(TX0/TX1/RX channels) SoC support in the
designware I2S driver and a flag to check if it is on the JH7110 SoC.
These channels need to enable clocks, resets and syscon register on the
JH7110 SoC. So add init ops in platform data for the JH7110 SoC to do this.
Their resets should be deassert before changing the parent of clocks so
these are done in the init ops of platform data.
The I2S controllers use DMA controller by platform data on the JH7110
and their settings about snd_dmaengine_dai_dma_data() should be added
in the dw_configure_dai_by_pd(). And use dmaengine PCM registration if
these do not have IRQ on the JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Link: https://lore.kernel.org/r/20230821144151.207339-4-xingyu.wu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add the StarFive JH7110 (TX0/TX1/RX channel) SoC support in the bindings
of Designware I2S controller. The I2S controller needs two reset items
to work properly on the JH7110 SoC. And TX0 channel as master mode needs
5 clock items and TX1/RX channels as slave mode need 9 clock items on
the JH7110 SoC. The RX channel needs System Register Controller property
to enable it and other platforms do not need it.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230821144151.207339-2-xingyu.wu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Current adg has default division for BRRA/BRRB, but it was created at
very beginning of the driver implementation, and is now an unnecessary
settings.
Because it has this default division, unexpected clockout might
be selected. For example if it requests only 44.1kHz base clockout,
unrequested 48kHz base clockout also will be selected.
This patch remove default division of clock out
Reported-by: Vincenzo De Michele <vincenzo.michele@davinci.de>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87il96zlep.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
DSP_SW_INTR_STAT_OFFSET is a common interrupt register which will be
accessed by both ACP firmware and driver. This register contains register
bits corresponds to host to dsp interrupts and vice versa.
when dsp to host interrupt is reported, only clear dsp to host
interrupt bit in DSP_SW_INTR_STAT_OFFSET.
Fixes: 2e7c6652f9 ("ASoC: SOF: amd: Fix for handling spurious interrupts from DSP")
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://lore.kernel.org/r/20230823073340.2829821-7-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Previously ACP SOF firmware used to enable the ACP external
global interrupt register.
This will restrict to report ACP host interrupts only after
firmware loading is successful.
This register needs to be set from host driver to handle
other ACP interrupts(SoundWire Interrupts) before loading
the ACP firmware.
Add field for external interrupt enable register in acp descriptor
structure and enable the external interrupt enable register.
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://lore.kernel.org/r/20230823073340.2829821-2-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
During initial development time for RN platform, when SHA
dma gets completed, SHA DMA engine used to raise the ACP interrupt.
In ACP interrupt handler, SHA DMA interrupt got handled.
Currently SHA DMA compleition is verified by checking
transfer count using read poll time out logic.
Remove unused SHA dma interrupt handling code.
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://lore.kernel.org/r/20230823073340.2829821-1-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add a new module parameter ipc4_ignore_cpc which can be used to force the
kernel to ignore the queried CPC value for all firmware modules and use 0
instead.
The CPC lookup is still done to report missing configurations and the
debug print is going to be different to be explicit that the CPC is ignored
and what was the value we would have used.
The CPC value is sent to the firmware with the MOD_INIT_INSTANCE message
and it is used by the firmware as a parameter for clock scaling.
The flag is intended to be used only when there is a need to validate the
firmware behavior regarding to clock scaling since the 0 CPC value will
force the DSP to run in full speed, disabling the scaling and provides
additional counter point to rule out clock management related issues.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Link: https://lore.kernel.org/r/20230822065419.24374-1-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge series from Peter Ujfalusi <peter.ujfalusi@linux.intel.com>:
The SRC component in a pipeline provides flexibility on the sampling
rate which was not handled previously. This series will improve the
kernel side with the needed logic to be able to deal with the SRC type
of components in pipelines.
The CS42L43 is an audio CODEC with integrated MIPI SoundWire interface
(Version 1.2.1 compliant), I2C, SPI, and I2S/TDM interfaces designed
for portable applications. It provides a high dynamic range, stereo
DAC for headphone output, two integrated Class D amplifiers for
loudspeakers, and two ADCs for wired headset microphone input or
stereo line input. PDM inputs are provided for digital microphones.
The ASoC component provides the majority of the functionality of the
device, all the audio functions.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230804104602.395892-7-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
