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Luca Weiss
308b26cddb arm64: dts: qcom: sdm632: Add device tree for Fairphone 3 
Add device tree for the Fairphone 3 smartphone which is based on
Snapdragon 632 (sdm632).

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220220201909.445468-11-luca@z3ntu.xyz
 2022-02-24 14:08:37 -06:00
Luca Weiss
cb898d5e59 dt-bindings: arm: qcom: Document sdm632 and fairphone,fp3 board 
Add binding documentation for Fairphone 3 smartphone which is based on
Snapdragon 632 (sm632).

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220220201909.445468-10-luca@z3ntu.xyz
 2022-02-24 14:08:37 -06:00
Vladimir Lypak
24af02271c arm64: dts: qcom: Add SDM632 device tree 
Snapdragon 632 is based on msm8953 with some minor differences, mostly
in the CPUs.

SDM632 is using Kryo 250 instead of ARM Cortex A53 and has some
differences in the thermal zones, mainly there being only one thermal
zones for the first 4 cores (efficiency cores) but keeps one thermal
zone per core for the remaining 4 cores (performance cores).

Co-developed-by: Gabriel David <ultracoolguy@disroot.org>
Signed-off-by: Gabriel David <ultracoolguy@disroot.org>
Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220220201909.445468-9-luca@z3ntu.xyz
 2022-02-24 14:08:37 -06:00
Vladimir Lypak
06ea71e429 arm64: dts: qcom: Add PM8953 PMIC 
Add a base DT for PM8953 PMIC, commonly used with MSM8953.

Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Rayyan Ansari <rayyan@ansari.sh>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220220201909.445468-8-luca@z3ntu.xyz
 2022-02-24 14:08:37 -06:00
Vladimir Lypak
9fb08c8019 arm64: dts: qcom: Add MSM8953 device tree 
Add a base DT for MSM8953 SoC.

Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Co-developed-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220220201909.445468-7-luca@z3ntu.xyz
 2022-02-24 14:08:36 -06:00
Luca Weiss
08b25f7d99 dt-bindings: arm: cpus: Add Kryo 250 CPUs 
Document Kryo 250 CPUs found in Qualcomm Snapdragon 632 (SDM632).

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220220201909.445468-5-luca@z3ntu.xyz
 2022-02-24 14:08:36 -06:00
Nikita Travkin
3016af34ef arm64: dts: qcom: msm8916-longcheer-l8150: Add light and proximity sensor 
L8150 uses LTR559 as a light and proximity sensor. Add it to the
devicetree.

Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220219145140.84712-1-nikita@trvn.ru
 2022-02-24 14:05:16 -06:00
Krzysztof Kozlowski
1e49defb86 arm64: dts: qcom: align Google CROS EC PWM node name with dtschema 
dtschema expects PWM node name to be a generic "pwm".  This also matches
Devicetree specification requirements about generic node names.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220214081916.162014-4-krzysztof.kozlowski@canonical.com
 2022-02-24 14:01:38 -06:00
Xilin Wu
d4b341269e arm64: dts: qcom: Add support for Samsung Galaxy Book2 
Add support for Samsung Galaxy Book2 (W737) tablets.

Currently working features:
- Bootloader preconfigured display at 1280p
- UFS
- Wacom Digitizer
- Two USB 3 ports
- Sound
- Bluetooth
- Wi-Fi

Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220223145130.544586-1-wuxilin123@gmail.com
 2022-02-23 23:24:16 -06:00
Dmitry Baryshkov
2b8c9c77c2 arm64: dts: qcom: msm8996: convert xo_board to RPM_SMD_BB_CLK1 
Convert all device tree xo_board users to the RPM_SMD_BB_CLK1 clock.
Note, that xo_board can not be removed (yet), as clk-smd-rpm uses
xo_board internally as the parent for all the clocks.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220215201539.3970459-6-dmitry.baryshkov@linaro.org
 2022-02-23 22:20:11 -06:00
Dmitry Baryshkov
79b9ced565 arm64: dts: qcom: msm8996: add cxo and sleep-clk to gcc node 
Supply proper cxo (RPM_SMD_BB_CLK1) and sleep_clk to the gcc clock
controller node.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220215201539.3970459-5-dmitry.baryshkov@linaro.org
 2022-02-23 22:20:11 -06:00
Dmitry Baryshkov
cfc090a0c9 arm64: dts: qcom: sdm845: add bi_tcxo to camcc 
Declare TCXO clock used for the Camera Clock Controller on SDM845.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220215201539.3970459-4-dmitry.baryshkov@linaro.org
 2022-02-23 22:20:11 -06:00
Vinod Koul
8f6e20adaa arm64: dts: qcom: sdm845: enable dma for spi 
Add dmas property for spi@880000 and pinconf setting so that we can use
dma for this spi device. Also, add iommu properties for qup and spi.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220222041951.1185186-2-vkoul@kernel.org
 2022-02-23 21:29:52 -06:00
Vinod Koul
29aed4b4eb arm64: dts: qcom: sdm845: Add gsi dma node 
This add the device node for gsi dma0 instances found in sdm845.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220222041951.1185186-1-vkoul@kernel.org
 2022-02-23 21:29:52 -06:00
Sibi Sankar
1e8853c698 arm64: dts: qcom: sc7280: Add cpu OPP tables 
Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1644428757-25575-1-git-send-email-quic_sibis@quicinc.com
 2022-02-23 13:11:36 -06:00
Odelu Kukatla
8b93fbd95e arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Acked-by: Georgi Djakov <djakov@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1634812857-10676-4-git-send-email-okukatla@codeaurora.org
 2022-02-23 13:10:32 -06:00
Sai Prakash Ranjan
1dc3e50eb6 arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node 
Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on SM8450
SoC.

Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/7995d003b77d5e066658af5b2cfa22ccb40b6cf7.1643355594.git.quic_saipraka@quicinc.com
 2022-02-10 18:31:05 -06:00
Kathiravan T
01b8c4aff3 arm64: dts: qcom: ipq6018: drop the clock-frequency property 
clock-frequency for IPQ6018 SoCs should be 24MHz, not 19.2MHz. Rather
than correcting it, drop the property itself since its already
configured by the bootloader.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1643819709-5410-3-git-send-email-quic_kathirav@quicinc.com
 2022-02-10 18:26:32 -06:00
Kathiravan T
555ab09c78 arm64: dts: qcom: ipq8074: drop the clock-frequency property 
Drop the clock-frequency property from the MMIO timer node, since it
is already configured by the bootloader.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1643819709-5410-2-git-send-email-quic_kathirav@quicinc.com
 2022-02-10 18:26:32 -06:00
Vinod Koul
aa2d0bf04a arm64: dts: qcom: sm8450: add interconnect nodes 
And the various interconnect nodes found in SM8450 SoC and use it for
UFS controller.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220203002936.3009402-1-vkoul@kernel.org
 2022-02-10 18:26:00 -06:00
Yassine Oudjana
b7072cc570 arm64: dts: qcom: qcs404: Rename CPU and CPR OPP tables 
Rename CPU and CPR OPP table node names to match the nodename pattern
defined in the opp-v2-base DT schema.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220203072226.51482-7-y.oudjana@protonmail.com
 2022-02-10 18:16:49 -06:00
Yassine Oudjana
f55dda2157 arm64: dts: qcom: msm8996: Rename cluster OPP tables 
Rename cluster OPP table node names to match the nodename pattern
defined in the opp-v2-base DT schema.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220203072226.51482-6-y.oudjana@protonmail.com
 2022-02-10 18:16:49 -06:00
Yassine Oudjana
3431a7f5bb arm64: dts: qcom: msm8996-mtp: Add msm8996 compatible 
Add qcom,msm8996 compatible to match DT schema.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220203072226.51482-3-y.oudjana@protonmail.com
 2022-02-10 18:16:49 -06:00
Yassine Oudjana
134cfc5565 dt-bindings: arm: qcom: Add msm8996 and apq8096 compatibles 
Add compatibles for MSM8996 and APQ8096 and all supported devices
that have them.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220203072226.51482-2-y.oudjana@protonmail.com
 2022-02-10 18:16:49 -06:00
Kathiravan T
3d44861d00 arm64: dts: qcom: ipq6018: enable the GICv2m support 
GIC used in the IPQ6018 SoCs has one instance of the GICv2m extension,
which supports upto 32 MSI interrupts. Lets add support for the same.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1644334525-11577-3-git-send-email-quic_kathirav@quicinc.com
 2022-02-10 18:12:05 -06:00
Kathiravan T
59892de947 arm64: dts: qcom: ipq8074: enable the GICv2m support 
GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension,
which supports upto 32 MSI interrupts. Lets add support for the same.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@quicinc.com
 2022-02-10 18:12:04 -06:00
Bjorn Andersson
ff899133fd arm64: dts: qcom: c630: Move panel to aux-bus 
With the newly introduced aux-bus under the TI SN65DSI86 the panel
node should be described as a child instead of a standalone node, move
it there.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Link: https://lore.kernel.org/r/20220208041606.144039-2-bjorn.andersson@linaro.org
 2022-02-08 15:24:59 -06:00
Bjorn Andersson
a28106a273 arm64: dts: qcom: c630: Add backlight controller 
The Lenovo Yoga C630 uses the PWM controller in the TI SN65DSI86 bridge
chip to provide a signal for the backlight control and has TLMM GPIO 11
attached to some regulator that drives the backlight.

Unfortunately the regulator attached to this gpio is also powering the
camera, so turning off backlight result in the detachment of the camera
as well.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Link: https://lore.kernel.org/r/20220208041606.144039-1-bjorn.andersson@linaro.org
 2022-02-08 15:24:59 -06:00
Douglas Anderson
116f7cc43d arm64: dts: qcom: sc7280: Add herobrine-r1 
Add the new herobrine-r1. Note that this is pretty much a re-design
compared to herobrine-r0 so we don't attempt any dtsi to share stuff
between them.

This patch attempts to define things at 3 levels:

1. The Qcard level. Herobrine includes a Qcard PCB and the Qcard PCB
   is supposed to be the same (modulo stuffing options) across
   multiple boards, so trying to define what's there hopefully makes
   sense. NOTE that newer "CRD" boards from Qualcomm also use
   Qcard. When support for CRD3 is added hopefully it can use the
   Qcard include (and perhaps we should even evaluate it using
   herobrine.dtsi?)
2. The herobrine "baseboard" level. Right now most stuff is here with
   the exception of things that we _know_ will be different per
   board. We know that not all boards will have the same set of eMMC,
   nvme, and SD. We also know that the exact pin names are likely to
   be different.
3. The actual "board" level, AKA herobrine-rev1.

NOTES:
- This boots to command prompt. We're still waiting on the PWM driver.
- This assumes LTE for now. Once it's clear how WiFi-only SKUs will
  work we expect some small changes.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220204140550.v4.1.I5604b7af908e8bbe709ac037a6a8a6ba8a2bfa94@changeid
 2022-02-04 16:29:45 -06:00
Vinod Koul
067b2b3616 arm64: dts: qcom: Add SM8450 HDK DTS 
This adds the base HDK DTS along with the usb, ufs and regulators found
in this board

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220203090031.3128702-2-vkoul@kernel.org
 2022-02-04 15:58:41 -06:00
Vinod Koul
42d3ce71eb dt-bindings: arm: qcom: Document SM8450 HDK boards 
Document the SM8450 HDK board

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220203090031.3128702-1-vkoul@kernel.org
 2022-02-04 15:58:40 -06:00
Douglas Anderson
96b34a6ea7 arm64: dts: qcom: sc7280: Add a blank line in the dp node 
It's weird that there's a blank line between the two port nodes but
not between the attributes and the first port node. Add an extra blank
line to make it look right.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.11.Iecb7267402e697a5cfef4cd517116ea5b308ac9e@changeid
 2022-02-04 15:53:33 -06:00
Douglas Anderson
ad4152d6e2 arm64: dts: qcom: sc7280: Move dp_hot_plug_det pull from SoC dtsi file 
Pulls should be in the board files, not in the SoC dtsi
file. Remove. Even though the sc7280 boards don't currently refer to
dp_hot_plug_det, let's re-add the pulls there just to keep this as a
no-op change. If boards don't need this / don't want it later then we
can remove it from them.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.10.Id346b23642f91e16d68d75f44bcdb5b9fbd155ea@changeid
 2022-02-04 15:53:33 -06:00
Douglas Anderson
376e9183c1 arm64: dts: qcom: sc7280: Move pcie1_clkreq pull / drive str to boards 
Pullups and drive strength don't belong in the SoC dtsi file. Move to
the board file.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.8.Iffff0c12440a047212a164601e637b03b9d2fc78@changeid
 2022-02-04 15:52:59 -06:00
Douglas Anderson
118cd3b8ec arm64: dts: qcom: sc7280: Add edp_out port and HPD lines 
Like dp_out, we should have defined edp_out in sc7280.dtsi so we don't
need to do this in the board files.

Like dp_hot_plug_det, we should define edp_hot_plug_det in
sc7280.dtsi.

We should set the default pinctrl for edp_hot_plug_det in
sc7280.dtsi. NOTE: this is _unlike_ the dp_hot_plug_det. It is
reasonable that in some boards the dedicated DP Hot Plug Detect will
not be hooked up in favor of Type C mechanisms. This is unlike eDP
where the Hot Plug Detect line (which functions as "panel ready" in
eDP) is highly likely to be used by boards.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.7.Ic84bb69c45be2fccf50e3bd17b845fe20eec624c@changeid
 2022-02-04 15:52:59 -06:00
Douglas Anderson
bbef2a9ca0 arm64: dts: qcom: sc7280: Fix sort order of dp_hot_plug_det / pcie1_clkreq_n 
The two nodes were mis-sorted. Reorder. This is a no-op change.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.6.I874c6f2a62b7922a33e10d390a8983219a76250b@changeid
 2022-02-04 15:52:59 -06:00
Douglas Anderson
8fdedd6c64 arm64: dts: qcom: sc7280-idp: No need for "input-enable" on sw_ctrl 
Specifying "input-enable" on a MSM GPIO is a no-op for the most
part. The only thing it really does is to explicitly force the output
of a GPIO to be disabled right at the point of a pinctrl
transition. We don't need to do this and we don't typically specify
"input-enable" unless there's a good reason to. Remove it.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.5.Ibaf8a803802beb089cc6266b37e6156cff3ddaec@changeid
 2022-02-04 15:52:59 -06:00
Douglas Anderson
f9800dde34 arm64: dts: qcom: sc7280: Clean up sdc1 / sdc2 pinctrl 
This patch makes a few improvements to the way that sdc1 / sdc2
pinctrl is specified on sc7280:

1. There's no reason to "group" the sdc pins into one overarching node
and there's a downside: we have to replicate the hierarchy in the
board device tree files. Let's clean this up.

2. There's really not a lot of reason not to list the "pinctrl" for
sdc1 (eMMC) in the SoC dtsi file. These aren't GPIO pins and
everyone's going to specify the same pins.

3. Even though it's likely that boards will need to override pinctrl
for sdc2 (SD card) to add the card detect GPIO, we can be symmetric
and add it to the SoC dsti file.

4. Let's get rid of the word "on" from the normal config and add a
"sleep" suffix to the sleep config. This looks cleaner to me.

This is intended to be a no-op change but it could plausibly change
behavior depending on how the pinctrl code parses things. One thing to
note is that "SD card detect" is explicitly listed now as keeping its
pull enabled in sleep since we still want to detect card insertions
even if the controller is suspended (because no card is inserted). The
pinctrl framework likely did this anyway, but it's nice to see it
explicit.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.4.I79baad7f52351aafb470f8b21a9fa79d7031ad6a@changeid
 2022-02-04 15:52:59 -06:00
Douglas Anderson
b1969bc522 arm64: dts: qcom: sc7280: Properly sort sdc pinctrl lines 
The sdc1 / sdc2 pinctrl lines were randomly stuffed in the middle of
the qup pinctrl lines. Sort them properly. This is a no-op
change. Just code movement.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.3.I6ae594129a8ad3d18af9f5ebffd895b4f6353a0a@changeid
 2022-02-04 15:52:59 -06:00
Douglas Anderson
7a86ac0405 arm64: dts: qcom: sc7280-herobrine: Consistently add "-regulator" suffix 
Some of the fixed regulators were missing the "-regulator" suffix. Add
it to be consistent within the file and consistent with the fixed
regulators in sc7180-trogdor.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.2.I627e60c5488d54a45fd1482ca19f0f6e45192db2@changeid
 2022-02-04 15:52:58 -06:00
Douglas Anderson
171bac4670 arm64: dts: qcom: sc7180-trogdor: Add "-regulator" suffix to pp3300_hub 
All of the other fixed regulators have the "-regulator" suffix. Add it
to pp3300_hub to match.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202132301.v3.1.I7b284531f1c992932f7eef8abaf7cc5548064f33@changeid
 2022-02-04 15:52:58 -06:00
Bjorn Andersson
72c370dfbd arm64: dts: qcom: sm8450-qrd: Enable remoteproc instances 
Enable the audio, compute, sensor and modem remoteproc and specify
firmware path for these on the Qualcomm SM8450 QRD.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220128025513.97188-14-bjorn.andersson@linaro.org
 2022-02-04 15:12:58 -06:00
Bjorn Andersson
1172729576 arm64: dts: qcom: sm8450: Add remoteproc enablers and instances 
The Qualcomm SM8450 carries the familiar set of audio, compute, sensor
and modem remoteprocs. Add these and their dependencies.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220128025513.97188-13-bjorn.andersson@linaro.org
 2022-02-04 15:12:57 -06:00
Alex Elder
73419e4d2f arm64: dts: qcom: add IPA qcom,qmp property 
At least three platforms require the "qcom,qmp" property to be
specified, so the IPA driver can request register retention across
power collapse.  Update DTS files accordingly.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220201140723.467431-1-elder@linaro.org
 2022-02-03 14:12:06 -06:00
Alexander Martinz
4588245915 arm64: dts: qcom: sdm845: add device tree for SHIFT6mq 
Add initial support for the SHIFT SHIFT6mq (axolotl) based on
the sdm845-mtp DT.

Currently supported features:
* Buttons (power, volume)
* Bluetooth, DSPs and modem
* Display and GPU
* Touch
* UART
* USB peripheral mode
* WLAN

Co-developed-by: Caleb Connolly <caleb@connolly.tech>
Signed-off-by: Caleb Connolly <caleb@connolly.tech>
Signed-off-by: Alexander Martinz <amartinz@shiftphones.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220123173650.290349-7-caleb@connolly.tech
 2022-01-31 18:30:55 -06:00
Caleb Connolly
12dfb002ca arm64: dts: qcom: sdm845-oneplus-*: add fuel gauge 
The OnePlus 6 and 6T feature a BQ27411 fuel gauge for reading the
battery stats. Enable it and add a simple battery to document the
battery specs of each device.

Signed-off-by: Caleb Connolly <caleb@connolly.tech>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220120184546.499030-1-caleb@connolly.tech
 2022-01-31 18:30:54 -06:00
Baruch Siach
d1c10ab149 arm64: dts: qcom: ipq6018: fix usb reference period 
Reference clock period for rate of 24MHz is 41ns (0x29).

Link: https://lore.kernel.org/r/1965fc315525b8ab26cf9f71f939c24d@codeaurora.org
Link: https://lore.kernel.org/r/a1932eba-564c-fe32-f220-53aa75250105@seco.com
Fixes: 20bb9e3dd2 ("arm64: dts: qcom: ipq6018: add usb3 DT description")
Reported-by: Kathiravan T <kathirav@codeaurora.org>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/4f4df55cf44cd0fd7d773aca171d4f48662fb1a5.1642704221.git.baruch@tkos.co.il
 2022-01-31 18:30:54 -06:00
Petr Vorel
8af90d6daa arm64: dts: qcom: msm8994-huawei-angler: Add vendor name huawei 
to follow the naming convention used by other DTS files.

Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220113233358.17972-5-petr.vorel@gmail.com
 2022-01-31 18:30:53 -06:00
Petr Vorel
4dd1ad6192 arm64: dts: qcom: msm8994: Provide missing "xo_board" and "sleep_clk" to GCC 
This is needed due changes in commit 0519d1d0bf ("clk: qcom:
gcc-msm8994: Modernize the driver"), which removed struct
clk_fixed_factor. Preparation for next commit for enabling SD/eMMC.
Inspired by 2c2f64ae36.

This is required for both msm8994-huawei-angler (sdhc1 will be enabled
in next commit) and msm8992-lg-bullhead (where actually fixes sdhc1
- tested on bullhead rev 1.01).

Fixes: 0519d1d0bf ("clk: qcom: gcc-msm8994: Modernize the driver")

Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220113233358.17972-4-petr.vorel@gmail.com
 2022-01-31 18:30:52 -06:00
Manivannan Sadhasivam
1b7101e812 arm64: dts: qcom: sm8250: Fix MSI IRQ for PCIe1 and PCIe2 
Fix the MSI IRQ used for PCIe instances 1 and 2.

Cc: stable@vger.kernel.org
Fixes: e53bdfc009 ("arm64: dts: qcom: sm8250: Add PCIe support")
Reported-by: Jordan Crouse <jordan@cosmicpenguin.net>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220112035556.5108-1-manivannan.sadhasivam@linaro.org
 2022-01-31 18:30:51 -06:00