Commit Graph

1294525 Commits

Author SHA1 Message Date
Bjorn Andersson
2cb4fcc4d9 Merge branch '20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr' into clk-for-6.12
Merge updates to MSM8998 GCC binding include file through topic branch,
to make available the newly added constants to both clock and DeviceTree
branch.
2024-08-15 16:10:24 -05:00
AngeloGioacchino Del Regno
015dff12df dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions
Add definitions for the Q6 BIMC, LPASS core and adsp smmu clocks,
required to enable audio functionality on MSM8998.

Add the GDSC definitions for the LPASS_ADSP_GDSC and LPASS_CORE_GDSC
as a final step to enable the required clock tree for the lpass iommu
and for the audio dsp itself.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 16:10:16 -05:00
Satya Priya Kakitapalli
82ceaf6bcd clk: qcom: Fix SM_CAMCC_8150 dependencies
SM_CAMCC_8150 depends on SM_GCC_8150, which inturn depends on ARM64.
Hence add the dependency to avoid below kernel-bot warning.

WARNING: unmet direct dependencies detected for SM_GCC_8150
Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n])
Selected by [y]:
- SM_CAMCC_8150 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y]

Fixes: ea73b7acef ("clk: qcom: Add camera clock controller driver for SM8150")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202408020234.jg9wrvhd-lkp@intel.com/
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240813085846.941855-1-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:55 -05:00
Satya Priya Kakitapalli
bab0c7a0bc clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src
The branch clocks of gcc_cpuss_ahb_clk_src are marked critical
and hence these clocks vote on XO blocking the suspend.
De-register these clocks and its source as there is no rate
setting happening on them.

Fixes: 4433594bbe ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: stable@vger.kernel.org
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-5-8b3eaa5fb856@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:55 -05:00
Satya Priya Kakitapalli
b8acaf2de8 clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table
Update the frequency tables of gcc_sdcc2_apps_clk and gcc_sdcc4_apps_clk
as per the latest frequency plan.

Fixes: 4433594bbe ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: stable@vger.kernel.org
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-4-8b3eaa5fb856@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:55 -05:00
Satya Priya Kakitapalli
818a2f8d5e clk: qcom: gcc-sc8180x: Add GPLL9 support
Add the missing GPLL9 pll and fix the gcc_parents_7 data to use
the correct pll hw.

Fixes: 4433594bbe ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: stable@vger.kernel.org
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-3-8b3eaa5fb856@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Satya Priya Kakitapalli
648b4bde0a dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x
Add the missing GPLL9 which is required for the gcc sdcc2 clock.

Fixes: 0fadcdfdcf ("dt-bindings: clock: Add SC8180x GCC binding")
Cc: stable@vger.kernel.org
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-2-8b3eaa5fb856@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Satya Priya Kakitapalli
1fc8c02e1d clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x
QUPv3 clocks support DFS on sc8180x platform but currently the code
changes for it are missing from the driver, this results in not
populating all the DFS supported frequencies and returns incorrect
frequency when the clients request for them. Hence add the DFS
registration for QUPv3 RCGs.

Fixes: 4433594bbe ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: stable@vger.kernel.org
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-1-8b3eaa5fb856@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Mike Tipton
a4e5af27e6 clk: qcom: clk-rpmh: Fix overflow in BCM vote
Valid frequencies may result in BCM votes that exceed the max HW value.
Set vote ceiling to BCM_TCS_CMD_VOTE_MASK to ensure the votes aren't
truncated, which can result in lower frequencies than desired.

Fixes: 04053f4d23 ("clk: qcom: clk-rpmh: Add IPA clock support")
Cc: stable@vger.kernel.org
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Reviewed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20240809-clk-rpmh-bcm-vote-fix-v2-1-240c584b7ef9@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Jagadeesh Kona
db30c1160c dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc
On SM8650, the minimum voltage corner supported on MMCX from cmd-db is
sufficient for clock controllers to operate and there is no need to specify
the required-opps. Hence remove the required-opps property from the list of
required properties for SM8650 camcc bindings.

This fixes:

arch/arm64/boot/dts/qcom/sm8650-hdk.dtb: clock-controller@ade0000:
'required-opps' is a required property

arch/arm64/boot/dts/qcom/sm8650-mtp.dtb: clock-controller@ade0000:
'required-opps' is a required property

arch/arm64/boot/dts/qcom/sm8650-qrd.dtb: clock-controller@ade0000:
'required-opps' is a required property

Fixes: 1ae3f0578e ("dt-bindings: clock: qcom: Add SM8650 camera clock controller")
Reported-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Closes: https://lore.kernel.org/all/0f13ab6b-dff1-4b26-9707-704ae2e2b535@linaro.org/
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202407070147.C9c3oTqS-lkp@intel.com/
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240801064448.29626-3-quic_jkona@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Jagadeesh Kona
6720e8dbcb dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc
On SM8650, the minimum voltage corner supported on MMCX from cmd-db is
sufficient for clock controllers to operate and there is no need to specify
the required-opps. Hence remove the required-opps property from the list of
required properties for SM8650 videocc bindings.

This fixes:

arch/arm64/boot/dts/qcom/sm8650-hdk.dtb: clock-controller@aaf0000:
'required-opps' is a required property

arch/arm64/boot/dts/qcom/sm8650-mtp.dtb: clock-controller@aaf0000:
'required-opps' is a required property

arch/arm64/boot/dts/qcom/sm8650-qrd.dtb: clock-controller@aaf0000:
'required-opps' is a required property

Fixes: a6a61b9701 ("dt-bindings: clock: qcom: Add SM8650 video clock controller")
Reported-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Closes: https://lore.kernel.org/all/0f13ab6b-dff1-4b26-9707-704ae2e2b535@linaro.org/
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202407070147.C9c3oTqS-lkp@intel.com/
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240801064448.29626-2-quic_jkona@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Rayyan Ansari
d0c2eccf64 dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema
Convert the bindings for the Turing Clock Controller on QCS404 from
the old text format to yaml.

Signed-off-by: Rayyan Ansari <rayyan.ansari@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240716085622.12182-2-rayyan.ansari@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Srinivas Kandagatla
386e0ac929 dt-bindings: clock: Add x1e80100 LPASSCC reset controller
X1E80100 LPASS (Low Power Audio Subsystem) clock controller provides reset
support when it is under the control of Q6DSP.

Add x1e80100 compatible to the existing sc8280xp as these reset
controllers have same reg layout and compatible.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240624-x1e-swr-reset-v2-2-8bc677fcfa64@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Srinivas Kandagatla
6319bdd24e dt-bindings: clock: Add x1e80100 LPASS AUDIOCC reset controller
X1E80100 LPASS (Low Power Audio Subsystem) Audio clock controller
provides reset support when it is under the control of Q6DSP.

Add x1e80100 compatible to the existing sc8280xp as these reset
controllers have same reg layout and compatible.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240624-x1e-swr-reset-v2-1-8bc677fcfa64@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Luca Weiss
fd1036f7a7 clk: qcom: a53-pll: Add MSM8226 a7pll support
The MSM8226 has one PLL for its Cortex-A7 cores. The frequencies will be
specified in devicetree.

Signed-off-by: Luca Weiss <luca@lucaweiss.eu>
Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-4-85143f5291d1@lucaweiss.eu
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Luca Weiss
76709d3538 dt-bindings: clock: qcom,a53pll: Add msm8226-a7pll compatible
Add the compatible for the A7PLL found in MSM8226 SoCs.

Signed-off-by: Luca Weiss <luca@lucaweiss.eu>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-3-85143f5291d1@lucaweiss.eu
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Luca Weiss
233ea1bda3 dt-bindings: clock: qcom,a53pll: Allow opp-table subnode
Allow placing an opp-table as a subnode that can be assigned using
operating-points-v2 to specify the frequency table for the PLL.

Signed-off-by: Luca Weiss <luca@lucaweiss.eu>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-2-85143f5291d1@lucaweiss.eu
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Ajit Pandey
d63c77c526 clk: qcom: Add GPUCC driver support for SM4450
Add Graphics Clock Controller (GPUCC) support for SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-8-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:49 -05:00
Ajit Pandey
ef40400767 clk: qcom: Add CAMCC driver support for SM4450
Add Camera Clock Controller (CAMCC) support for SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-6-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:22 -05:00
Ajit Pandey
76f05f1ec7 clk: qcom: Add DISPCC driver support for SM4450
Add Display Clock Controller (DISPCC) support for SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-4-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:13:57 -05:00
Ajit Pandey
fff617979f clk: qcom: clk-alpha-pll: Fix CAL_L_VAL override for LUCID EVO PLL
In LUCID EVO PLL CAL_L_VAL and L_VAL bitfields are part of single
PLL_L_VAL register. Update for L_VAL bitfield values in PLL_L_VAL
register using regmap_write() API in __alpha_pll_trion_set_rate
callback will override LUCID EVO PLL initial configuration related
to PLL_CAL_L_VAL bit fields in PLL_L_VAL register.

Observed random PLL lock failures during PLL enable due to such
override in PLL calibration value. Use regmap_update_bits() with
L_VAL bitfield mask instead of regmap_write() API to update only
PLL_L_VAL bitfields in __alpha_pll_trion_set_rate callback.

Fixes: 260e36606a ("clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces")
Cc: stable@vger.kernel.org
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-2-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14 21:07:28 -05:00
Bjorn Andersson
b4c71885e5 Merge branch '20240611133752.2192401-1-quic_ajipan@quicinc.com' into clk-for-6.12
Merge the SM4450 display, camera and GPU bindings through a topic
branch, to make it possible to merge them into the DeviceTree source
branch as well.
2024-08-14 21:05:26 -05:00
Ajit Pandey
47bad234ee dt-bindings: clock: qcom: add GPUCC clocks on SM4450
Add device tree bindings for the graphics clock controller on
Qualcomm SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-7-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14 21:05:15 -05:00
Ajit Pandey
9bf45e4f31 dt-bindings: clock: qcom: add CAMCC clocks on SM4450
Add device tree bindings for the camera clock controller on
Qualcomm SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-5-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14 21:05:15 -05:00
Ajit Pandey
5115bcaf68 dt-bindings: clock: qcom: add DISPCC clocks on SM4450
Add device tree bindings for the display clock controller on
Qualcomm SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-3-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14 21:05:15 -05:00
Bjorn Andersson
e997b400c8 clk: qcom: camcc-sm8150: Correct qcom_cc_really_probe() argument
The SM8150 Camera Clock controller was merged using the old arguments
for qcom_cc_really_probe(), correct this.

Fixes: ea73b7acef ("clk: qcom: Add camera clock controller driver for SM8150")
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-04 20:46:49 -05:00
Dmitry Baryshkov
802b832055 clk: qcom: fold dispcc-sm8650 info dispcc-sm8550
There is a very minor difference between display clock controller
drivers for SM8550 and SM8650 platforms. Fold the second one into the
first one to reduce kernel footprint. The bindings for these two
hardware blocks are fully compatible.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-6-5c4a3128c40b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 22:10:03 -05:00
Dmitry Baryshkov
c8bee3ff6c clk: qcom: dispcc-sm8550: use rcg2_shared_ops for ESC RCGs
Follow the recommendations and park disp_cc_mdss_esc[01]_clk_src to the
XO instead of disabling the clocks by using the clk_rcg2_shared_ops.

Fixes: 90114ca114 ("clk: qcom: add SM8550 DISPCC driver")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-5-5c4a3128c40b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 22:08:33 -05:00
Dmitry Baryshkov
7de10ddbdb clk: qcom: dispcc-sm8650: Update the GDSC flags
Add missing POLL_CFG_GDSCR to the MDSS GDSC flags.

Fixes: 90114ca114 ("clk: qcom: add SM8550 DISPCC driver")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-4-5c4a3128c40b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 22:08:33 -05:00
Dmitry Baryshkov
eb64ccacd0 clk: qcom: dispcc-sm8550: make struct clk_init_data const
The clk_init_data instances are not changed at runtime. Mark them as
constant data.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-3-5c4a3128c40b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 22:08:33 -05:00
Dmitry Baryshkov
cb4c00698f clk: qcom: dispcc-sm8550: use rcg2_ops for mdss_dptx1_aux_clk_src
clk_dp_ops should only be used for DisplayPort pixel clocks. Use
clk_rcg2_ops for disp_cc_mdss_dptx1_aux_clk_src.

Fixes: 90114ca114 ("clk: qcom: add SM8550 DISPCC driver")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-2-5c4a3128c40b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 22:08:33 -05:00
Dmitry Baryshkov
7b6a4b9072 clk: qcom: dispcc-sm8550: fix several supposed typos
Fix seveal odd-looking places in SM8550's dispcc driver:

- duplicate entries in disp_cc_parent_map_4 and disp_cc_parent_map_5
- using &disp_cc_mdss_dptx0_link_div_clk_src as a source for
  disp_cc_mdss_dptx1_usb_router_link_intf_clk

The SM8650 driver has been used as a reference.

Fixes: 90114ca114 ("clk: qcom: add SM8550 DISPCC driver")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-1-5c4a3128c40b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 22:08:33 -05:00
Bjorn Andersson
d9b66d8300 Merge branch '20240717-dispcc-sm8550-fixes-v2-7-5c4a3128c40b@linaro.org' into clk-for-6.12
Merge the SM8550/SM8650 display clock controller binding header file
merge through a topic branch, to ensure the bindings are kept in sync
between clock and DeviceTree source branches.
2024-07-31 22:05:44 -05:00
Dmitry Baryshkov
99447ef003 dt-bindings: clock: qcom,sm8650-dispcc: replace with symlink
The display clock controller indices for SM8650 and SM8550 are
completely equal. Replace the header file for qcom,sm8650-dispcc with
the symlink to the qcom,sm8550-dispcc header file.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-7-5c4a3128c40b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 22:05:25 -05:00
Satya Priya Kakitapalli
ea73b7acef clk: qcom: Add camera clock controller driver for SM8150
Add support for the camera clock controller for camera clients
to be able to request for camcc clocks on SM8150 platform.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240731062916.2680823-8-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 21:57:02 -05:00
Taniya Das
0c31f6a3ab clk: qcom: clk-alpha-pll: Add support for Regera PLL ops
Regera PLL ops are required to control the Regera PLL from clock
controller drivers, hence add the Regera PLL ops and configure
function.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240731062916.2680823-6-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 21:57:02 -05:00
Bjorn Andersson
a689c2961f Merge branch '20240731062916.2680823-7-quic_skakitap@quicinc.com' into clk-for-6.12
Merge SM8150 camera clock controller binding through topic branch, to
allow this to be shared with DeviceTree source branches as well.
2024-07-31 21:53:59 -05:00
Satya Priya Kakitapalli
44933cd06e dt-bindings: clock: qcom: Add SM8150 camera clock controller
Add device tree bindings for the camera clock controller on
Qualcomm SM8150 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240731062916.2680823-7-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 21:53:47 -05:00
Bjorn Andersson
a5652d05f8 clk: qcom: gcc-sc8180x: Add missing USB MP resets
The USB multiport controller needs a few additional resets, add these to
the driver.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240730-sc8180x-usb-mp-v2-2-a7dc4265b553@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 21:51:03 -05:00
Bjorn Andersson
856d6c2769 Merge branch '20240730-sc8180x-usb-mp-v2-1-a7dc4265b553@quicinc.com' into clk-for-6.12
Merge the sc8180x multiport reset DeviceTree constants through a topic
branch, to allow them also to be made available to DeviceTree source.
2024-07-31 21:49:50 -05:00
Bjorn Andersson
39b5ffc955 dt-bindings: clock: qcom: Add missing USB MP resets
The USB multiport controller needs a few missing resets, describe them
in the binding.

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20240730-sc8180x-usb-mp-v2-1-a7dc4265b553@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31 21:48:16 -05:00
Manivannan Sadhasivam
889e133231 clk: qcom: gcc-sm8450: Do not turn off PCIe GDSCs during gdsc_disable()
With PWRSTS_OFF_ON, PCIe GDSCs are turned off during gdsc_disable(). This
can happen during scenarios such as system suspend and breaks the resume
of PCIe controllers from suspend.

So use PWRSTS_RET_ON to indicate the GDSC driver to not turn off the GDSCs
during gdsc_disable() and allow the hardware to transition the GDSCs to
retention when the parent domain enters low power state during system
suspend.

Cc: stable@vger.kernel.org # 5.17
Fixes: db0c944ee9 ("clk: qcom: Add clock driver for SM8450")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240722105733.13040-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-28 22:15:22 -05:00
Manivannan Sadhasivam
ade508b545 clk: qcom: gcc-sm8250: Do not turn off PCIe GDSCs during gdsc_disable()
With PWRSTS_OFF_ON, PCIe GDSCs are turned off during gdsc_disable(). This
can happen during scenarios such as system suspend and breaks the resume
of PCIe controllers from suspend.

So use PWRSTS_RET_ON to indicate the GDSC driver to not turn off the GDSCs
during gdsc_disable() and allow the hardware to transition the GDSCs to
retention when the parent domain enters low power state during system
suspend.

Cc: stable@vger.kernel.org # 5.7
Fixes: 3e5770921a ("clk: qcom: gcc: Add global clock controller driver for SM8250")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240719134238.312191-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-28 22:15:22 -05:00
Christophe JAILLET
da3c15ea05 clk: qcom: Constify struct freq_tbl
'struct freq_tbl' are not modified in these drivers.

Constifying this structure moves some data to a read-only section, so
increase overall security.

On a x86_64, with allmodconfig, as an example:
Before:
======
   text	   data	    bss	    dec	    hex	filename
   7595	  43696	      0	  51291	   c85b	drivers/clk/qcom/mmcc-apq8084.o

After:
=====
   text	   data	    bss	    dec	    hex	filename
   9867	  41424	      0	  51291	   c85b	drivers/clk/qcom/mmcc-apq8084.o

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/e8aee66fa83a4e65f7e855eb8bdbc91275d6994b.1720962107.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-28 21:41:48 -05:00
Linus Torvalds
8400291e28 Linux 6.11-rc1 v6.11-rc1 2024-07-28 14:19:55 -07:00
Linus Torvalds
a0c04bd55a Merge tag 'kbuild-fixes-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild
Pull Kbuild fixes from Masahiro Yamada:

 - Fix RPM package build error caused by an incorrect locale setup

 - Mark modules.weakdep as ghost in RPM package

 - Fix the odd combination of -S and -c in stack protector scripts,
   which is an error with the latest Clang

* tag 'kbuild-fixes-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild:
  kbuild: Fix '-S -c' in x86 stack protector scripts
  kbuild: rpm-pkg: ghost modules.weakdep file
  kbuild: rpm-pkg: Fix C locale setup
2024-07-28 14:02:48 -07:00
Linus Torvalds
017fa3e891 minmax: simplify and clarify min_t()/max_t() implementation
This simplifies the min_t() and max_t() macros by no longer making them
work in the context of a C constant expression.

That means that you can no longer use them for static initializers or
for array sizes in type definitions, but there were only a couple of
such uses, and all of them were converted (famous last words) to use
MIN_T/MAX_T instead.

Cc: David Laight <David.Laight@aculab.com>
Cc: Lorenzo Stoakes <lorenzo.stoakes@oracle.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2024-07-28 13:50:01 -07:00
Linus Torvalds
4477b39c32 minmax: add a few more MIN_T/MAX_T users
Commit 3a7e02c040 ("minmax: avoid overly complicated constant
expressions in VM code") added the simpler MIN_T/MAX_T macros in order
to avoid some excessive expansion from the rather complicated regular
min/max macros.

The complexity of those macros stems from two issues:

 (a) trying to use them in situations that require a C constant
     expression (in static initializers and for array sizes)

 (b) the type sanity checking

and MIN_T/MAX_T avoids both of these issues.

Now, in the whole (long) discussion about all this, it was pointed out
that the whole type sanity checking is entirely unnecessary for
min_t/max_t which get a fixed type that the comparison is done in.

But that still leaves min_t/max_t unnecessarily complicated due to
worries about the C constant expression case.

However, it turns out that there really aren't very many cases that use
min_t/max_t for this, and we can just force-convert those.

This does exactly that.

Which in turn will then allow for much simpler implementations of
min_t()/max_t().  All the usual "macros in all upper case will evaluate
the arguments multiple times" rules apply.

We should do all the same things for the regular min/max() vs MIN/MAX()
cases, but that has the added complexity of various drivers defining
their own local versions of MIN/MAX, so that needs another level of
fixes first.

Link: https://lore.kernel.org/all/b47fad1d0cf8449886ad148f8c013dae@AcuMS.aculab.com/
Cc: David Laight <David.Laight@aculab.com>
Cc: Lorenzo Stoakes <lorenzo.stoakes@oracle.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2024-07-28 13:41:14 -07:00
Linus Torvalds
7e2d0ba732 Merge tag 'ubifs-for-linus-6.11-rc1-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs
Pull UBI and UBIFS updates from Richard Weinberger:

 - Many fixes for power-cut issues by Zhihao Cheng

 - Another ubiblock error path fix

 - ubiblock section mismatch fix

 - Misc fixes all over the place

* tag 'ubifs-for-linus-6.11-rc1-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs:
  ubi: Fix ubi_init() ubiblock_exit() section mismatch
  ubifs: add check for crypto_shash_tfm_digest
  ubifs: Fix inconsistent inode size when powercut happens during appendant writing
  ubi: block: fix null-pointer-dereference in ubiblock_create()
  ubifs: fix kernel-doc warnings
  ubifs: correct UBIFS_DFS_DIR_LEN macro definition and improve code clarity
  mtd: ubi: Restore missing cleanup on ubi_init() failure path
  ubifs: dbg_orphan_check: Fix missed key type checking
  ubifs: Fix unattached inode when powercut happens in creating
  ubifs: Fix space leak when powercut happens in linking tmpfile
  ubifs: Move ui->data initialization after initializing security
  ubifs: Fix adding orphan entry twice for the same inode
  ubifs: Remove insert_dead_orphan from replaying orphan process
  Revert "ubifs: ubifs_symlink: Fix memleak of inode->i_link in error path"
  ubifs: Don't add xattr inode into orphan area
  ubifs: Fix unattached xattr inode if powercut happens after deleting
  mtd: ubi: avoid expensive do_div() on 32-bit machines
  mtd: ubi: make ubi_class constant
  ubi: eba: properly rollback inside self_check_eba
2024-07-28 11:51:51 -07:00
Nathan Chancellor
3415b10a03 kbuild: Fix '-S -c' in x86 stack protector scripts
After a recent change in clang to stop consuming all instances of '-S'
and '-c' [1], the stack protector scripts break due to the kernel's use
of -Werror=unused-command-line-argument to catch cases where flags are
not being properly consumed by the compiler driver:

  $ echo | clang -o - -x c - -S -c -Werror=unused-command-line-argument
  clang: error: argument unused during compilation: '-c' [-Werror,-Wunused-command-line-argument]

This results in CONFIG_STACKPROTECTOR getting disabled because
CONFIG_CC_HAS_SANE_STACKPROTECTOR is no longer set.

'-c' and '-S' both instruct the compiler to stop at different stages of
the pipeline ('-S' after compiling, '-c' after assembling), so having
them present together in the same command makes little sense. In this
case, the test wants to stop before assembling because it is looking at
the textual assembly output of the compiler for either '%fs' or '%gs',
so remove '-c' from the list of arguments to resolve the error.

All versions of GCC continue to work after this change, along with
versions of clang that do or do not contain the change mentioned above.

Cc: stable@vger.kernel.org
Fixes: 4f7fd4d7a7 ("[PATCH] Add the -fstack-protector option to the CFLAGS")
Fixes: 60a5317ff0 ("x86: implement x86_32 stack protector")
Link: 6461e53781 [1]
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2024-07-29 03:47:00 +09:00