Stephen Boyd
270bbc7253
Merge branches 'clk-doc', 'clk-renesas', 'clk-at91', 'clk-cleanup' and 'clk-debugfs' into clk-next
...
* clk-doc:
clk: Gemini: fix struct name in kernel-doc
clk: zynq: pll: Fix kernel-doc warnings
clk: imx: pllv1: fix kernel-doc notation for struct clk_pllv1
* clk-renesas: (31 commits)
clk: renesas: r9a07g044: Add GPU clock and reset entries
clk: renesas: r9a07g044: Add mux and divider for G clock
clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
clk: renesas: cpg-mssr: Add support for R-Car S4-8
clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver
dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779f0 SYSC power domain definitions
clk: renesas: r9a07g044: Add TSU clock and reset entry
mmc: renesas_sdhi: Simplify an expression
mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock
dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0
clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()
clk: renesas: cpg-mssr: Check return value of pm_genpd_init()
clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()
clk: renesas: rzg2l: Check return value of pm_genpd_init()
clk: renesas: r9a07g044: Add RSPI clock and reset entries
clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
mmc: renesas_sdhi: Parse DT for SDnH
mmc: renesas_sdhi: Use dev_err_probe when getting clock fails
...
* clk-at91:
clk: lan966x: Extend lan966x clock driver for clock gating support
dt-bindings: clock: lan966x: Extend includes with clock gates
dt-bindings: clock: lan966x: Extend for clock gate support
clk: gate: Add devm_clk_hw_register_gate()
clk: lan966x: Add lan966x SoC clock driver
dt-bindings: clock: lan966x: Add LAN966X Clock Controller
dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs
* clk-cleanup:
clk: stm32mp1: remove redundant assignment to pointer data
clk: __clk_core_init() never takes NULL
clk: clk_core_get() can also return NULL
clk/ti/adpll: Make const pointer error a static const array
* clk-debugfs:
clk: Enable/Disable runtime PM for clk_summary
clk: Emit a stern warning with writable debugfs enabled
clk: Add write operation for clk_parent debugfs node
2022-01-11 18:30:10 -08:00
Taniya Das
1bb294a798
clk: Enable/Disable runtime PM for clk_summary
...
The registers for some clocks in the SOC area, which are under the power
domain are required to be enabled before accessing them. During the
clk_summary if the power-domains are not enabled they could result into
NoC errors.
Thus ensure the register access of the clock controller is done with
pm_untime_get/put functions.
Signed-off-by: Taniya Das <tdas@codeaurora.org >
Link: https://lore.kernel.org/r/1640018638-19436-3-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-01-05 17:20:23 -08:00
Stephen Boyd
a5ce1d5118
Merge tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
...
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add GPU clock and resets on Renesas RZ/G2L
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a07g044: Add GPU clock and reset entries
clk: renesas: r9a07g044: Add mux and divider for G clock
clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
clk: renesas: cpg-mssr: Add support for R-Car S4-8
clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver
dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779f0 SYSC power domain definitions
2021-12-28 21:42:12 -08:00
Colin Ian King
d66e4c985d
clk: stm32mp1: remove redundant assignment to pointer data
...
The pointer data is being initialized with a value and a few lines
later on being re-assigned the same value, so this re-assignment is
redundant. Clean up the code and remove it.
Signed-off-by: Colin Ian King <colin.i.king@gmail.com >
Link: https://lore.kernel.org/r/20211126221239.1100960-1-colin.i.king@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-12-15 22:48:28 -08:00
Stephen Boyd
489a71964f
clk: Emit a stern warning with writable debugfs enabled
...
We don't want vendors to be enabling this part of the clk code and
shipping it to customers. Exposing the ability to change clk frequencies
and parents via debugfs is potentially damaging to the system if folks
don't know what they're doing. Emit a strong warning so that the message
is clear: don't enable this outside of development systems.
Fixes: 37215da555geert+renesas@glider.be >
Link: https://lore.kernel.org/r/20211210014237.2130300-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-12-10 15:19:35 -08:00
Sam Protsenko
a331659e32
clk: Add write operation for clk_parent debugfs node
...
Useful for testing mux clocks. One can write the index of the parent to
be set into clk_parent node, starting from 0. Example
# cd /sys/kernel/debug/clk/mout_peri_bus
# cat clk_possible_parents
dout_shared0_div4 dout_shared1_div4
# cat clk_parent
dout_shared0_div4
# echo 1 > clk_parent
# cat clk_parent
dout_shared1_div4
CLOCK_ALLOW_WRITE_DEBUGFS has to be defined in drivers/clk/clk.c in
order to use this feature.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org >
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com >
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be >
Reviewed-by: Fabio Estevam <festevam@gmail.com >
Acked-by: Michael Turquette <mturquette@baylibre.com >
Link: https://lore.kernel.org/r/20211013172042.10884-1-semen.protsenko@linaro.org
[sboyd@kernel.org: Collapse ifdefs]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-12-09 17:27:24 -08:00
Stephen Boyd
978fbc7a05
clk: __clk_core_init() never takes NULL
...
The only caller of __clk_core_init() allocates the pointer and checks
the allocation for NULL so this check is impossible. Remove it.
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
Link: https://lore.kernel.org/r/20211208041534.3928718-2-sboyd@kernel.org
2021-12-09 17:15:47 -08:00
Stephen Boyd
5c1c42c49b
clk: clk_core_get() can also return NULL
...
Nothing stops a clk controller from registering an OF clk provider
before registering those clks with the clk framework. This is not great
but we deal with it in the clk framework by refusing to hand out struct
clk pointers when 'hw->core' is NULL, the indication that clk_register()
has been called.
Within clk_core_fill_parent_index() we considered this case when a
clk_hw pointer is referenced directly by filling in the parent cache
with an -EPROBE_DEFER pointer when the core pointer is NULL. When we
lookup a parent with clk_core_get() we don't care about the return value
being NULL though, because that was considered largely impossible, but
it's been proven now that it can be NULL if two clk providers are
probing in parallel and the parent provider has been registered before
the clk has. Let's check for NULL here as well and treat it the same as
direct clk_hw references.
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
Link: https://lore.kernel.org/r/20211208041534.3928718-1-sboyd@kernel.org
2021-12-09 17:15:47 -08:00
Colin Ian King
9259228037
clk/ti/adpll: Make const pointer error a static const array
...
Make const pointer error a static const array, removes a dereference
and shrinks object code a little.
Signed-off-by: Colin Ian King <colin.i.king@gmail.com >
Link: https://lore.kernel.org/r/20211127173036.150535-1-colin.i.king@gmail.com
Acked-by: Tony Lindgren <tony@atomide.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-12-09 17:15:15 -08:00
Stephen Boyd
8f6b28c5b1
Merge tag 'clk-at91-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-at91
...
Pull AT91 clk driver updates from Nicolas Ferre:
- Lan966x Generic Clock Controller driver and associated DT bindings
- Lan966x clock driver extended to support clock gating
* tag 'clk-at91-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
clk: lan966x: Extend lan966x clock driver for clock gating support
dt-bindings: clock: lan966x: Extend includes with clock gates
dt-bindings: clock: lan966x: Extend for clock gate support
clk: gate: Add devm_clk_hw_register_gate()
clk: lan966x: Add lan966x SoC clock driver
dt-bindings: clock: lan966x: Add LAN966X Clock Controller
dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs
2021-12-09 00:28:39 -08:00
Horatiu Vultur
5ad5915dea
clk: lan966x: Extend lan966x clock driver for clock gating support
...
Extend the clock driver to add support also for clock gating. The
following peripherals can be gated: UHPHS, UDPHS, MCRAMC, HMATRIX.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com >
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Link: https://lore.kernel.org/r/20211103085102.1656081-5-horatiu.vultur@microchip.com
2021-12-08 11:19:20 +01:00
Horatiu Vultur
51d0a37dde
dt-bindings: clock: lan966x: Extend includes with clock gates
...
On lan966x it is allow to control the clock to some peripherals like
USB. So extend the include file with these clocks.
Acked-by: Rob Herring <robh@kernel.org >
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com >
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Link: https://lore.kernel.org/r/20211103085102.1656081-4-horatiu.vultur@microchip.com
2021-12-08 11:19:20 +01:00
Horatiu Vultur
6b9f984cc8
dt-bindings: clock: lan966x: Extend for clock gate support
...
Allow to add an optional resource to be able to access the clock gate
registers.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com >
Acked-by: Rob Herring <robh@kernel.org >
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Link: https://lore.kernel.org/r/20211103085102.1656081-3-horatiu.vultur@microchip.com
2021-12-08 11:19:20 +01:00
Horatiu Vultur
815f0e738a
clk: gate: Add devm_clk_hw_register_gate()
...
Add devm_clk_hw_register_gate() - devres-managed version of
clk_hw_register_gate()
Suggested-by: Stephen Boyd <sboyd@kernel.org >
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com >
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchip.com
2021-12-08 11:19:20 +01:00
Kavyasree Kotagiri
54104ee023
clk: lan966x: Add lan966x SoC clock driver
...
This adds Generic Clock Controller driver for lan966x SoC.
Lan966x clock controller contains 3 PLLs - cpu_clk, ddr_clk
and sys_clk. It generates and supplies clock to various
peripherals within SoC.
Register settings required to provide GCK clocking to a
peripheral is as below:
GCK_SRC_SEL = Select clock source.
GCK_PRESCALER = Set divider value.
GCK_ENA = 1 - Enable GCK clock.
Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com >
Co-developed-by: Horatiu Vultur <horatiu.vultur@microchip.com >
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com >
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Link: https://lore.kernel.org/r/20211103061935.25677-4-kavyasree.kotagiri@microchip.com
2021-12-08 10:57:26 +01:00
Kavyasree Kotagiri
07300ef47a
dt-bindings: clock: lan966x: Add LAN966X Clock Controller
...
This adds the DT bindings documentation for lan966x SoC
generic clock controller.
Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com >
Reviewed-by: Rob Herring <robh@kernel.org >
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Link: https://lore.kernel.org/r/20211103061935.25677-3-kavyasree.kotagiri@microchip.com
2021-12-08 10:57:26 +01:00
Kavyasree Kotagiri
265d27caf9
dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs
...
LAN966X supports 14 clock outputs for its peripherals.
This include file is introduced to use identifiers for clocks.
Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com >
Acked-by: Rob Herring <robh@kernel.org >
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com >
Link: https://lore.kernel.org/r/20211103061935.25677-2-kavyasree.kotagiri@microchip.com
2021-12-08 10:57:25 +01:00
Biju Das
f0b62b0bbe
clk: renesas: r9a07g044: Add GPU clock and reset entries
...
Add GPU clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211203115154.31864-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-12-08 10:05:56 +01:00
Biju Das
7ef9c45a23
clk: renesas: r9a07g044: Add mux and divider for G clock
...
G clock is sourced from PLL3 and PLL6. The output of the mux is
connected to divider.
This patch adds a mux and divider for getting different rates from
this clock sources.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211203115154.31864-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-12-08 10:05:56 +01:00
Biju Das
98ee8b2f66
clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
...
Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree
mentioned in the hardware manual(Rev.1.00 Sep, 2021).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211203115154.31864-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-12-08 10:05:56 +01:00
Yoshihiro Shimoda
24aaff6a6c
clk: renesas: cpg-mssr: Add support for R-Car S4-8
...
Initial CPG support for R-Car S4-8 (r8a779f0).
Inspired by patches in the BSP by LUU HOAI.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com >
Link: https://lore.kernel.org/r/20211201073308.1003945-10-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-12-08 10:05:56 +01:00
Geert Uytterhoeven
39cf7dd21d
Merge tag 'renesas-r8a779f0-dt-binding-defs-tag' into HEAD
...
Renesas R-Car S4-8 DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car S4-8 (R8A77FA0)
SoC, shared by driver and DT source files.
2021-12-08 10:05:50 +01:00
Yoshihiro Shimoda
470e3f0d0b
clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver
...
According to the official website [1], the R-Car V3U SoC is based
on the R-Car Gen4 architecture. So, introduce R-Car Gen4 CPG
driver.
[1]
https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com >
Link: https://lore.kernel.org/r/20211201073308.1003945-9-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-12-08 10:05:22 +01:00
Stephen Boyd
1dfeb03e86
Merge tag 'renesas-clk-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
...
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
thermal (TSU) clocks and resets on RZ/G2L
- Rework SDHI clock handling in the R-Car Gen3 and RZ/G2 clock
drivers, and in the Renesas SDHI driver
- Make the Cortex-A55 (I) clock on RZ/G2L programmable,
- Document support for the new R-Car S4-8 (R8A779F0) SoC
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (24 commits)
clk: renesas: r9a07g044: Add TSU clock and reset entry
mmc: renesas_sdhi: Simplify an expression
mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock
dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0
clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()
clk: renesas: cpg-mssr: Check return value of pm_genpd_init()
clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()
clk: renesas: rzg2l: Check return value of pm_genpd_init()
clk: renesas: r9a07g044: Add RSPI clock and reset entries
clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
mmc: renesas_sdhi: Parse DT for SDnH
mmc: renesas_sdhi: Use dev_err_probe when getting clock fails
clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST
clk: renesas: rcar-gen3: Switch to new SD clock handling
mmc: renesas_sdhi: Flag non-standard SDnH handling for V3M
clk: renesas: r8a779a0: Add SDnH clock to V3U
clk: renesas: rcar-gen3: Add SDnH clock
clk: renesas: rcar-gen3: Add dummy SDnH clock
clk: renesas: r9a07g044: Add OSTM clock and reset entries
...
2021-12-07 20:16:36 -08:00
Yoshihiro Shimoda
81c1655823
dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
...
Add all Clock Pulse Generator Core Clock Outputs for the Renesas
R-Car S4-8 (R8A779F0) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com >
Link: https://lore.kernel.org/r/20211201073308.1003945-4-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-12-07 16:29:25 +01:00
Yoshihiro Shimoda
500daa0e6b
dt-bindings: power: Add r8a779f0 SYSC power domain definitions
...
Add power domain indices for R-Car S4-8 (r8a779f0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com >
Link: https://lore.kernel.org/r/20211201073308.1003945-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-12-07 16:29:24 +01:00
Randy Dunlap
ecb64bbff7
clk: Gemini: fix struct name in kernel-doc
...
Fix a typo in the struct name in the kernel-doc notation so that
kernel-doc won't complain about it.
Fixes this warning:
drivers/clk/clk-gemini.c:64: warning: expecting prototype for struct gemini_data_data. Prototype was for struct gemini_gate_data instead
Fixes: 846423f967rdunlap@infradead.org >
Reported-by: kernel test robot <lkp@intel.com >
Cc: linux-clk@vger.kernel.org
Link: https://lore.kernel.org/r/20211120062719.21395-1-rdunlap@infradead.org
Reviewed-by: Linus Walleij <linus.walleij@linaro.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-12-02 17:27:48 -08:00
Shubhrajyoti Datta
8a3492cd8d
clk: zynq: pll: Fix kernel-doc warnings
...
Fix the following kernel-doc warning
drivers/clk/zynq/pll.c:15: warning: missing initial short description on line:
* struct zynq_pll
drivers/clk/zynq/pll.c:96: warning: No description found for return value of 'zynq_pll_is_enabled'
drivers/clk/zynq/pll.c:116: warning: No description found for return value of 'zynq_pll_enable'
drivers/clk/zynq/pll.c:187: warning: No description found for return value of 'clk_register_zynq_pll'
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com >
Link: https://lore.kernel.org/r/9929a56462bfdd491c43c233abc4341fc14dac1d.1637139796.git.shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-12-02 17:27:24 -08:00
Randy Dunlap
71e7623161
clk: imx: pllv1: fix kernel-doc notation for struct clk_pllv1
...
Convert struct clk_pllv1 comments to kernel-doc notation and move them
below the MFN_* macros.
Fixes this kernel-doc warning:
drivers/clk/imx/clk-pllv1.c:12: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* pll v1
Fixes: 2af9e6db14a594790368rdunlap@infradead.org >
Reported-by: kernel test robot <lkp@intel.com >
Cc: Abel Vesa <abel.vesa@nxp.com >
Cc: linux-clk@vger.kernel.org
Cc: linux-imx@nxp.com
Cc: Alexander Shiyan <shc_work@mail.ru >
Cc: Shawn Guo <shawn.guo@linaro.org >
Cc: Sascha Hauer <s.hauer@pengutronix.de >
Link: https://lore.kernel.org/r/20211115032607.28970-1-rdunlap@infradead.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-12-02 17:26:40 -08:00
Biju Das
33b22d9c32
clk: renesas: r9a07g044: Add TSU clock and reset entry
...
Add TSU clock and reset entry to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211120180438.8351-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-26 14:06:16 +01:00
Wolfram Sang
45177fc641
mmc: renesas_sdhi: Simplify an expression
...
We already have 'quirks', no need to go via 'priv'.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Acked-by: Ulf Hansson <ulf.hansson@linaro.org >
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se >
Link: https://lore.kernel.org/r/20211117103850.28397-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-26 14:06:16 +01:00
Geert Uytterhoeven
366df82fc6
mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock
...
Use the existing devm_clk_get_optional() helper to obtain the optional
Card Detect clock, instead of open-coding the same operation.
a side effect, real errors will now be handled correctly instead of
being ignored.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Acked-by: Ulf Hansson <ulf.hansson@linaro.org >
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/540d803d31bf9aa1d0f78f431cae0ccd05387edc.1637069733.git.geert+renesas@glider.be
2021-11-26 14:04:16 +01:00
Yoshihiro Shimoda
827fbac821
dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0
...
Add binding documentation for the R-Car S4-8 (R8A779F0) Clock Pulse
Generator.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com >
Link: https://lore.kernel.org/r/20211116074130.107554-7-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:40:52 +01:00
Lad Prabhakar
97c8d514af
clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()
...
of_genpd_add_provider_simple() might fail, this patch makes sure we check
the return value of of_genpd_add_provider_simple() by propagating the
return value to the caller of cpg_mssr_add_clk_domain().
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211117115101.28281-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:40:02 +01:00
Lad Prabhakar
fa58e46554
clk: renesas: cpg-mssr: Check return value of pm_genpd_init()
...
Make sure we check the return value of pm_genpd_init() which might fail.
Also add a devres action to remove the power-domain in-case the probe
callback fails further down in the code flow.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211117115101.28281-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:40:02 +01:00
Lad Prabhakar
33748744f1
clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()
...
of_genpd_add_provider_simple() might fail, this patch makes sure we check
the return value of of_genpd_add_provider_simple() by propagating the
return value to the caller of rzg2l_cpg_add_clk_domain().
Fixes: ef3c613ccdprabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211117115101.28281-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:37:03 +01:00
Lad Prabhakar
27527a3d3b
clk: renesas: rzg2l: Check return value of pm_genpd_init()
...
Make sure we check the return value of pm_genpd_init() which might fail.
Also add a devres action to remove the power-domain in-case the probe
callback fails further down in the code flow.
Fixes: ef3c613ccdprabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211117115101.28281-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:37:03 +01:00
Lad Prabhakar
e7d960cd6a
clk: renesas: r9a07g044: Add RSPI clock and reset entries
...
Add RSPI{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com >
Link: https://lore.kernel.org/r/20211117002601.17971-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:36:27 +01:00
Biju Das
d6dabaf678
clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
...
Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual
Rev.1.00.
This patch adds clock divider table "dtable_1_8" and switches to
DEF_DIV for "I" clock.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211112081003.15453-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:34:56 +01:00
Biju Das
86e122c075
clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
...
Core clock "I" is sourced from CPG_PL1_DDIV which controls CPU
frequency. Define CPG_PL1_DDIV, so that we can register it as a
clock divider in later patch.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211112081003.15453-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:34:56 +01:00
Wolfram Sang
e5f7e81ee4
mmc: renesas_sdhi: Parse DT for SDnH
...
If there is a SDnH clock provided in DT, let's use it instead of relying
on the fallback.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Acked-by: Ulf Hansson <ulf.hansson@linaro.org >
Link: https://lore.kernel.org/r/20211110191610.5664-21-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:32:39 +01:00
Wolfram Sang
079e83b958
mmc: renesas_sdhi: Use dev_err_probe when getting clock fails
...
This is to improve deferred probe in this driver and to keep consistent
with an up-to-date handling of a soon to be added second clock.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Acked-by: Ulf Hansson <ulf.hansson@linaro.org >
Link: https://lore.kernel.org/r/20211110191610.5664-20-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:32:39 +01:00
Wolfram Sang
d3a52bc41d
clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST
...
We handle it differently meanwhile.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/20211110191610.5664-7-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:32:39 +01:00
Wolfram Sang
bb6d3fa98a
clk: renesas: rcar-gen3: Switch to new SD clock handling
...
The old SD handling code was huge and could not handle all the details
which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to
another design. Have SDnH a separate clock, use the existing divider
clocks and move the errata handling from the clock driver to the SDHI
driver where it belongs.
This patch removes the old SD handling code and switch to the new one.
This updates the SDHI driver at the same time. Because the SDHI driver
can only communicate with the clock driver via clk_set_rate(), I don't
see an alternative to this flag-day-approach, so we cross subsystems
here.
The patch sadly looks messy for the CPG lib, but it is basically a huge
chunk of code removed and smaller chunks added. It looks much better
when you just view the resulting source file.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Acked-by: Ulf Hansson <ulf.hansson@linaro.org > # For MMC
Link: https://lore.kernel.org/r/20211110191610.5664-6-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:32:39 +01:00
Wolfram Sang
627151b496
mmc: renesas_sdhi: Flag non-standard SDnH handling for V3M
...
V3M handles SDnH differently than other Gen3 SoCs, so let's add a
separate entry for that. This will allow better SDnH handling in the
future.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Acked-by: Ulf Hansson <ulf.hansson@linaro.org >
Link: https://lore.kernel.org/r/20211110191610.5664-5-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:32:17 +01:00
Wolfram Sang
63494b6f98
clk: renesas: r8a779a0: Add SDnH clock to V3U
...
Currently a pass-through clock but we will make it a real divider clock
in the next patches.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/20211110191610.5664-4-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:27:58 +01:00
Wolfram Sang
1abd044808
clk: renesas: rcar-gen3: Add SDnH clock
...
Currently a pass-through clock but we will make it a real divider clock
in the next patches.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/20211110191610.5664-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:27:58 +01:00
Wolfram Sang
a31cf51bf6
clk: renesas: rcar-gen3: Add dummy SDnH clock
...
Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a separate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/20211110191610.5664-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-19 11:27:58 +01:00
Biju Das
161450134a
clk: renesas: r9a07g044: Add OSTM clock and reset entries
...
Add OSTM{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211110082019.28554-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-15 10:47:18 +01:00
Biju Das
dc446cba43
clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros
...
Rename the macros CLK_PLL2_DIV16->CLK_PLL2_DIV2_8 and
CLK_PLL2_DIV20->CLK_PLL2_DIV2_10 to match the clock tree mentioned in
the hardware manual(Rev.1.00 Sep, 2021).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20211110082019.28554-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-11-15 10:47:18 +01:00
