Commit Graph

1335631 Commits

Author SHA1 Message Date
Philip Yang
23b645231e drm/amdgpu: Unlocked unmap only clear page table leaves
SVM migration unmap pages from GPU and then update mapping to GPU to
recover page fault. Currently unmap clears the PDE entry for range
length >= huge page and free PTB bo, update mapping to alloc new PT bo.
There is race bug that the freed entry bo maybe still on the pt_free
list, reused when updating mapping and then freed, leave invalid PDE
entry and cause GPU page fault.

By setting the update to clear only one PDE entry or clear PTB, to
avoid unmap to free PTE bo. This fixes the race bug and improve the
unmap and map to GPU performance. Update mapping to huge page will
still free the PTB bo.

With this change, the vm->pt_freed list and work is not needed. Add
WARN_ON(unlocked) in amdgpu_vm_pt_free_dfs to catch if unmap to free the
PTB.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:05:49 -05:00
Alex Deucher
1350dd3691 drm/amdgpu/mes11: fix set_hw_resources_1 calculation
It's GPU page size not CPU page size.  In most cases they
are the same, but not always.  This can lead to overallocation
on systems with larger pages.

Cc: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:05:49 -05:00
Eric Huang
5ffd56822a drm/amdkfd: fix missing L2 cache info in topology
In some ASICs L2 cache info may miss in kfd topology,
because the first bitmap may be empty, that means
the first cu may be inactive, so to find the first
active cu will solve the issue.

v2: Only find the first active cu in the first xcc

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:05:49 -05:00
Alex Deucher
ebc25499de drm/amdgpu/vcn2.5: split code along instances
Split the code on a per instance basis.  This will allow
us to use the per instance functions in the future to
handle more things per instance.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:05:49 -05:00
Taimur Hassan
53472eeb22 drm/amd/display: 3.2.320
Summary:

* Start enabling support for 4-plane MPO
* DML21 Updates
* SPL Updates
* Other minor fixes

Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:05:49 -05:00
Harish Kasiviswanathan
3394b1f76d drm/amdgpu: Set snoop bit for SDMA for MI series
SDMA writes has to probe invalidate RW lines. Set snoop bit in mmhub for
this to happen.

v2: Missed a few mmhub_v9_4. Added now.
v3: Calculate hub offset once since it doesn't change inside the loop
    Modified function names based on review comments.

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:05:49 -05:00
Samson Tam
53b2e0c24a drm/amd/display: sspl: cleanup filter code
[Why & How]
Remove unused filters and functions
Add static to limit scope

Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:05:48 -05:00
Aurabindo Pillai
8f87447a8e drm/amd/display: Make dcn401_program_pipe non static
Allow reuse of code by making dcn401_program_pipe()
non static.

Fixes: 2739bd1237 ("drm/amd/display: Allow reuse of of DCN4x code")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:10 -05:00
Charlene Liu
b40d022ec0 drm/amd/display: pass calculated dram_speed_mts to dml2
[why]
currently dml2 is using a hard coded 16 to convert memclk to dram_speed_mts.
for apu, this depends on wck_ratio.

change to pass the already calculated dram_speed_mts from fpu to dml2.

v2: use existing calculation of dram_speed_mts for now to avoid regression

Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:10 -05:00
Brendan Tam
51d1b33854 drm/amd/display: add workaround flag to link to force FFE preset
[Why]
There have been instances of some monitors being unable to link train on
their reported link speed using their selected FFE preset. If a different
FFE preset is found that has a higher rate of success during link training
this workaround can be used to force its FFE preset.

[How]
A new link workaround flag is made called force_dp_ffe_preset. The flag is
checked in override_training_settings and will set lt_settings->ffe_preset
which is null if the flag is not set. The flag is then set in
override_lane_settings.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Brendan Tam <Brendan.Tam@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Samson Tam
5a20ca32a2 drm/amd/display: add s1_12 filter tables
[Why & How]
Instead of converting tables from s1_10 to s1_12, add s1_12 tables instead.
Remove init calls that do the conversion. Add APIs to read s1_10 tables

Reviewed-by: Navid Assadian <navid.assadian@amd.com>
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Ausef Yousof
c36d7948bb drm/amd/display: limit coverage of optimization skip
[why&how]
causing some regression on dgpu which still needs the
pre-emptive return, limit this to reporter asic version
it is simple to include
different dcn versions from this point forward, each dcn
resource is initialized with the flag and can be enabled
at will

Reviewed-by: Chris Park <chris.park@amd.com>
Signed-off-by: Ausef Yousof <Ausef.Yousof@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Leo Zeng
b474a6e11f drm/amd/display: add new IRQ enum for underflows
[WHY & HOW]
needed in certain scenarios for debugging and logging

Reviewed-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Leo Zeng <Leo.Zeng@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Samson Tam
2a4519c4e9 drm/amd/display: remove TF check for LLS policy
[Why & How]
LLS policy not affected by TF.
Remove check in don't care case and use
 pixel format only.

Reviewed-by: Navid Assadian <navid.assadian@amd.com>
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Samson Tam
8e539d2dd2 drm/amd/display: use s1_12 filter tables in SPL
[Why & How]
Instead of converting tables from s1_10 to s1_12,
 added s1_12 tables instead in SPL
Remove init calls that do the conversion

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Austin Zheng
1b30456150 drm/amd/display: DML21 Reintegration
For various fixes to mcache_row_bytes calculation.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Ilya Bakoulin
e8bffa52e0 drm/amd/display: Don't try AUX transactions on disconnected link
[Why]
Setting link DPMS off in response to HPD disconnect creates AUX
transactions on a link that is supposed to be disconnected. This can
cause issues in some cases when the sink re-asserts HPD and expects
source to re-enable the link.

[How]
Avoid AUX transactions on disconnected link.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Zaeem Mohamed
fed4c27537 drm/amd/display: docstring definitions MAX_SURFACES and MAX_PLANES
MAX_SURFACES and MAX_PLANES now have docstrings that better show the difference between the two.

Reviewed-by: Sun peng Li <sunpeng.li@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Zaeem Mohamed
14d7ca5273 drm/amd/display: Expose 3 secondary planes for supported ASICs
[why]
For enabling 4-plane MPO, we need dc to expose 4 planes for DCN35 and
beyond, as well as DCN21

[how]
Set dc_caps.max_slave_*planes to 3 for appropriate ASICs

Reviewed-by: Sun peng Li <sunpeng.li@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Tim Huang
76e0410fe0 drm/amdgpu: add discovery support for DCN IP version 3.6.0
Add discovery entry for DCN IP version 3.6.0.

Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Mario Limonciello
0a0bd4f95c drm/amd: Refactor find_system_memory()
find_system_memory() pulls out two fields from an SMBIOS type 17
device and sets them on KFD devices. The data offsets are counted
to find interesting data.

Instead use a struct representation to access the members and pull
out the two specific fields.

No intended functional changes.

Link: https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.8.0.pdf p99
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Link: https://lore.kernel.org/r/20250206214847.3334595-1-superm1@kernel.org
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:09 -05:00
Jiang Liu
e92f3f94ca drm/amdgpu: reset psp->cmd to NULL after releasing the buffer
Reset psp->cmd to NULL after releasing the buffer in function psp_sw_fini().

Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Jiang Liu <gerry@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Asad Kamal
aafe181f7d drm/amdgpu: Add flags to distinguish vf/pf/pt mode
Add extra flag definition for ids_flag field to distinguish
between vf/pf/pt modes

v2: Updated kms driver minor version & removed pf check as default is 0
v3: Fix up version (Alex)
v4: rebase (Alex)

Proposed userspace:
e663bed7d6

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Alex Deucher
759e764f7d drm/amdkfd: use GTT for VRAM on APUs only if GTT is larger
If the user has configured a large carveout on a small APU,
only use GTT for VRAM allocations if GTT is larger than
VRAM.

v2: fix reversed check (Philip)

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Alex Deucher
8b0d068e7d drm/amdkfd: add a new flag to manage where VRAM allocations go
On big and small APUs we send KFD VRAM allocations to GTT
since the carve out is either non-existent or relatively
small.  However, if someone sets the carve out size to be
relatively large, we may end up using GTT rather than VRAM.

No change of logic with this patch, but it allows the
driver to determine which logic to use based on the
carve out size in the future.

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Lijo Lazar
cc0e91a755 drm/amdgpu: Make VBIOS image read optional
Keep VBIOS image read optional for select SOCs in passthrough mode.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Lijo Lazar
6e8ca38ebc drm/amdgpu: Add flag to make VBIOS read optional
Certain SOCs may not need much data from VBIOS. Some data like VBIOS
version used will be missed but it doesn't affect functionality. Add a
flag to make VBIOS image optional.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Lijo Lazar
7e0aa70681 drm/amdgpu: Add VBIOS flags
Instead of read_bios, use get_bios_flags to get various options around
reading VBIOS.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Lijo Lazar
e986e89659 drm/amdgpu: Add wrapper for freeing vbios memory
Use bios_release wrapper to release memory allocated for vbios image and
reset the variables.

v2:
	Use the same wrapper for clean up in sw_fini (Alex Deucher)

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Wayne Lin
1846a3472f drm/amd/display: Add DCN36 DM Support
Add DM handling for DCN36.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Wayne Lin
4bc8f12db2 drm/amd/display: Add DCN36 CORE
Add DCN36 support in dc_resource.c.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Wayne Lin
9b7d816f09 drm/amd/display: Support DCN36 HDCP
Add case in hdcp_create_workqueue() to support HDCP on DCN36 as well.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Wayne Lin
23577b3a15 drm/amd/display: Support DCN36 DSC
Add case on clean_up_dsc_blocks() to support DCN36 as well.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:08 -05:00
Wayne Lin
c5dd47d9e6 drm/amd/display: Add DCN36 DMCUB
DMCU-B (Display Micro-Controller Unit B) is a display microcontroller
used for shared display functionality with BIOS and for advanced
power saving display features.

Add case to support DCN3.6 as well.

V2: adjust copyright license text

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:07 -05:00
Wayne Lin
8cb06693bc drm/amd/display: Add DCN36 DML2 support
Enable DML2 for DCN36.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:07 -05:00
Wayne Lin
4bcba9844b drm/amd/display: Add DCN36 GPIO
Add DCN36 support in GPIO.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:07 -05:00
Wayne Lin
9ae42f6120 drm/amd/display: Add DCN36 Resource
Add resource handling for DCN36.

V2: adjust copyright license text
V3: remove unnecessary headers

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:07 -05:00
Wayne Lin
76e3b62db9 drm/amd/display: Add DCN36 IRQ
Add IRQ services for DCN36.
This allows us to create/init and manage irqs for DCN3

V2: adjust copyright license text

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:07 -05:00
Wayne Lin
02efc0a780 drm/amd/display: Add DCN36 BIOS command table support
Add case for DCN36 in command_table_helper2.c.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:07 -05:00
Wayne Lin
59f79d83fc drm/amd/display: Add DCN36 version identifiers
Add DCN3.6 asic identifiers.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:07 -05:00
Wayne Lin
9b194af117 drm/amd/display: Add dcn36 register header files
[Why & How]
Add register headers for DCN36.

V2: adjust copyright license text

Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:07 -05:00
Alex Deucher
15f00b073c drm/amdgpu/gfx9: use amdgpu_gfx_off_ctrl_immediate() for PG
Use amdgpu_gfx_off_ctrl_immediate() when powergating.
There's no need for the delay in gfx off allow.  The
powergating is dynamically disabled/enabled as for
RV/PCO on compute queues and allowing gfx off again as
soon the job is submitted improves power savings.

Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Suggested-by: Błażej Szczygieł <mumei6102@gmail.com>
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3861
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:07 -05:00
Alex Deucher
250d9769ee drm/amdgpu/gfx: add amdgpu_gfx_off_ctrl_immediate()
Same as amdgpu_gfx_off_ctrl(), but without the delay
for gfxoff disallow.

Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Suggested-by: Błażej Szczygieł <mumei6102@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:07 -05:00
Shaoyun Liu
1c687c0da9 drm/amd/include : MES v11 and v12 API header update
MES requires driver set cleaner_shader_fence_mc_addr
for cleaner shader support.

Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:06 -05:00
Lijo Lazar
a53cbd9e6f drm/amd/pm: Remove unnecessary device state checks
For amdgpu_get_pp_force_state, amdgpu_get_pp_cur_state already takes
care of device state check. In other cases, values are returned from
driver cached variables and are not dependent on device state.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <feifei.xu@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:06 -05:00
Lijo Lazar
543f6e7163 drm/amd/pm: Fix get_if_active usage
If a device supports runtime pm, then pm_runtime_get_if_active returns 0
if a device is not active and 1 if already active. However, if a device
doesn't support runtime pm, the API returns -EINVAL. A device not
supporting runtime pm implies it's not affected by runtime pm and it's
active. Hence no need to get() to increment usage count. Remove < 0
return value check. Also, ignore runpm state to determine active status.
If the device is already in suspend state, disallow access.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <feifei.xu@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:06 -05:00
Lijo Lazar
55aa33c3fe drm/amd/pm: Add APIs for device access checks
Wrap the checks before device access in helper functions and use them
for device access. The generic order of APIs now is to do input argument
validation first and check if device access is allowed.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <feifei.xu@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:06 -05:00
Lijo Lazar
a5219b41dd drm/amdgpu: Clean up atom header file inclusion
atom bios header files are not required in these files.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:06 -05:00
Alex Deucher
abab978127 drm/amdgpu/sdma4: drop gfxoff calls in dump ip state
SDMA 4.x is not part of the GFX power domain so this is
not necessary.

Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:04:06 -05:00
Alex Hung
3e7ef261d3 drm/amd/display: Replace pr_info in dc_validate_boot_timing()
Use DC_LOG_DEBUG instead of pr_info to match other uses in dc.c.

Fixes: 091e301c2b ("drm/amd/display: Add debug messages for dc_validate_boot_timing()")
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12 21:03:03 -05:00