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Sam Protsenko
0b76bdce32 dt-bindings: phy: samsung,usb3-drd-phy: Add Exynos850 support 
Document Exynos850 compatible. USB 2.0 DRD PHY on Exynos850 has two
clocks (ref and phy), which is already described in bindings.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230819031731.22618-3-semen.protsenko@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:41:15 +05:30
Dmitry Baryshkov
b83eb8ba2a phy: qcom-qmp-combo: fix clock probing 
During rebase of qcom-qmp-combo series a call to devm_clk_bulk_get_all()
got moved by git from qmp_combo_parse_dt_legacy() to
phy_dp_clks_register(). This doesn't have any serious effect, since the
clocks will be set in both legacy and non-legacy paths. However let's
move it back to place anyway, to prevent the driver from fetching clocks
twice.

Fixes: 28e265bf84 ("phy: qcom-qmp-combo: simplify clock handling")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820235813.562284-1-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:35:13 +05:30
Dmitry Baryshkov
4807ff70e2 phy: qcom-qmp-pcie: support SM8150 PCIe QMP PHYs 
Reuse sm8250 configuration to add support for both single lane and dual
lane PCIe PHYs on the Qualcomm SM8150 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-8-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:33:37 +05:30
Dmitry Baryshkov
bf46fa1daf phy: qcom-qmp-pcie: populate offsets configuration 
Populate offsets configuration for the rest of UFS PHYs to make it
possible to switch them to the new (single-node) bindings style.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-7-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:33:37 +05:30
Dmitry Baryshkov
067832dc03 phy: qcom-qmp-pcie: simplify clock handling 
For some of existing PHYs for new binding we are going to change refgen
to more correct "rchng". Rather than introducing additional code
to handle legacy vs current bindings (and clock names), use
devm_clk_bulk_get_optional().

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-6-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:33:37 +05:30
Dmitry Baryshkov
86f703762a phy: qcom-qmp-pcie: keep offset tables sorted 
In order to simplify adding new PHY configurations, keep register
offset structs sorted by the version.

Fixes: a05b6d5135 ("phy: qcom-qmp-pcie: add support for sa8775p")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-5-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:33:37 +05:30
Dmitry Baryshkov
cfe0d20381 phy: qcom-qmp-pcie: drop ln_shrd from v5_20 config 
There is no shared lane config for v5.20 PHYs, it is only present on
SM8550 gen4x2.

Fixes: a05b6d5135 ("phy: qcom-qmp-pcie: add support for sa8775p")
Cc: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-4-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:33:37 +05:30
Dmitry Baryshkov
377107bcc6 dt-bindings: phy: qcom,qmp-pcie: describe SM8150 PCIe PHYs 
Descrbie two PCIe PHYs found on the Qualcomm SM8150 platform, single
lane and two lanes Gen3 PHYs.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-3-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:33:37 +05:30
Dmitry Baryshkov
505fb25416 dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml 
Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml)
to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare
the child PHY node or split resource regions.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:33:37 +05:30
Alexander Stein
9f266c1c73 phy: fsl-imx8mq-usb: add dev_err_probe if getting vbus failed 
This adds an error message if getting vbus failed for some reason,
-EPROBE_DEFER is handled appropriately as well and adds a nice
information to debugfs.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Link: https://lore.kernel.org/r/20230816080256.611380-1-alexander.stein@ew.tq-group.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:28:11 +05:30
Varadarajan Narayanan
08e49af507 phy: qcom: Introduce M31 USB PHY driver 
Add the M31 USB2 phy driver for the USB M31 PHY
(https://www.m31tech.com) found in Qualcomm IPQ5018, IPQ5332
SoCs.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/c8821bb0124a54cc774a2ff7b9c40df28eb7711e.1691999761.git.quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:28:11 +05:30
Varadarajan Narayanan
f444491ccd dt-bindings: phy: qcom,m31: Document qcom,m31 USB phy 
Document the M31 USB2 phy present in IPQ5332.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/44a31cf0361df8db527684c7fb3b38e6ece950c1.1691999761.git.quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:28:11 +05:30
Jagan Teki
dfe44a1377 phy: rockchip: inno-dsidphy: Add rv1126 support 
Add support for Rockchip RV1126 DSI-DPHY.

The existing 2.5GHz phy timing table added for RK3568 is working
as it is for RV1126 as well.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20230731110012.2913742-5-jagan@edgeble.ai
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:28:11 +05:30
Jagan Teki
e92681b376 dt-bindings: phy: rockchip-inno-dsidphy: Document rv1126 
Document a compatible string for the rv1126 dsi-dphy.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230731110012.2913742-4-jagan@edgeble.ai
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:28:10 +05:30
Eugen Hristev
188a447b20 dt-bindings: phy: mediatek,tphy: allow simple nodename pattern 
The pattern for the nodename only allows t-phy@... , however, for the case
when the t-phy has no `reg` and only `ranges` (basically when the t-phy
is just a parent node), dtc will throw this warning:

Warning (unit_address_vs_reg): /t-phy@1a243000: node has a unit name, but no reg or ranges property

For a node like this:

	sata_phy: t-phy@1a243000 {
		ranges;

		sata_port: sata-phy@1a243000 {
			reg = <0 0x1a243000 0 0x0100>;
		};
	};

it is normal that the parent node 't-phy' would be without any address, as in:

	sata_phy: t-phy {
		ranges;

		sata_port: sata-phy@1a243000 {
			reg = <0 0x1a243000 0 0x0100>;
		};
	};

because being just a holder it does not have its own reg.

However the binding does not allow such a name for the t-phy, so with this
patch, making the `@[0-9a-f]+` part optional, such node is possible.

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230814093931.9298-1-eugen.hristev@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:28:10 +05:30
Krzysztof Kozlowski
ffc1786c3f phy: amlogic: meson-g12a-usb2: fix Wvoid-pointer-to-enum-cast warning 
'soc_id' is an enum, thus cast of pointer on 64-bit compile test with
W=1 causes:

  phy-meson-g12a-usb2.c:322:17: error: cast to smaller integer type 'enum meson_soc_id' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast]

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230810091310.70231-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-22 19:28:10 +05:30
Krzysztof Kozlowski
7451eecf1e phy: marvell pxa-usb: fix Wvoid-pointer-to-enum-cast warning 
'version' is an enum, thus cast of pointer on 64-bit compile test with
W=1 causes:

  phy-pxa-usb.c:299:26: error: cast to smaller integer type 'enum pxa_usb_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast]

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230810111958.205705-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-11 09:25:15 +01:00
Krzysztof Kozlowski
2bc00b9b90 phy: broadcom: sr-usb: fix Wvoid-pointer-to-enum-cast warning 
'version' is an enum, thus cast of pointer on 64-bit compile test with
W=1 causes:

  phy-bcm-sr-usb.c:314:13: error: cast to smaller integer type 'enum bcm_usb_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast]

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230810111958.205705-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-11 09:25:14 +01:00
Krzysztof Kozlowski
bd6e74a2f0 phy: broadcom: ns-usb3: fix Wvoid-pointer-to-enum-cast warning 
'family' is an enum, thus cast of pointer on 64-bit compile test with
W=1 causes:

  drivers/phy/broadcom/phy-bcm-ns-usb3.c:209:17: error: cast to smaller integer type 'enum bcm_ns_family' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast]

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230810111958.205705-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-11 09:25:14 +01:00
Krzysztof Kozlowski
d35c12b7db phy: broadcom: sata: fix Wvoid-pointer-to-enum-cast warning 
'version' is an enum, thus cast of pointer on 64-bit compile test with
W=1 causes:

  phy-brcm-sata.c:775:19: error: cast to smaller integer type 'enum brcm_sata_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast]

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230810111958.205705-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-11 09:25:14 +01:00
Rohit Agarwal
aff7625322 dt-bindings: phy: qcom,snps-eusb2-repeater: Add compatible for PM7550BA 
Add a dt-bindings compatible string for the Qualcomm's PM7550BA PMIC.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1691415534-31820-2-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-11 09:23:04 +01:00
Lukas Bulwahn
6ac1bb8695 MAINTAINERS: correct file entry in STARFIVE JH7110 DPHY RX DRIVER 
Commit f8aa660841 ("phy: starfive: Add mipi dphy rx support") adds the
MAINTAINERS section STARFIVE JH7110 DPHY RX DRIVER referring to
'phy-starfive-dphy-rx.c', but the file actually added in this commit is
named 'phy-jh7110-dphy-rx.c'.

Correct the file entry in STARFIVE JH7110 DPHY RX DRIVER.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Link: https://lore.kernel.org/r/20230731114856.14401-1-lukas.bulwahn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-11 09:19:12 +01:00
Dmitry Baryshkov
b102ce6d84 phy: qcom: qmp-ufs: add missing offsets to sm8150 configuration 
The conversion commit 7559e7572c ("phy: Explicitly include correct DT
includes") misses offsets configuration for sm8150 (most likely it was
developed separately from the series adding HS G4 support and was not
adapted for the sm8150/sm8250 configuration split).

Add missing offsets to sm8150_ufsphy_cfg.

Fixes: 7559e7572c ("phy: Explicitly include correct DT includes")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230731111009.3998089-1-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-08-11 09:17:19 +01:00
Geert Uytterhoeven
e7379477f4 phy: starfive: StarFive PHYs should depend on ARCH_STARFIVE 
The various StarFive PHYs are only present on StarFive SoCs.  Hence add
a dependency on ARCH_STARFIVE, to prevent asking the user about these
drivers when configuring a kernel without StarFive SoC support.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Link: https://lore.kernel.org/r/12097f6107a18e2f7cfb80f47ac7b27808e062c4.1690300076.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-26 19:09:08 +05:30
Vinod Koul
ec6beb8258 phy: starfive: make phys depend on HAS_IOMEM 
the startfive phy drivers use devm_platform_ioremap_resource() which on
some archs (s390) is not present. So make the drivers depend on HAS_IOMEM

Fixes: f8aa660841 ("phy: starfive: Add mipi dphy rx support")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202307250509.oeudxG28-lkp@intel.com/
Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20230725063856.482696-1-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-25 19:22:11 +05:30
Dmitry Baryshkov
486392f44d phy: qcom-qmp-combo: add qcom,sc7280-qmp-usb3-dp-phy compat entry 
Add separate device entry for Combo USB+DP QMP PHY on sc7280 platform.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230711120916.4165894-5-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-24 16:25:39 +05:30
Dmitry Baryshkov
a542ae82df phy: qcom-qmp-combo: populate offsets for all combo PHYs 
In order to support newer style bindings for combo PHYs, populate
offsets for all Combo QMP PHY configurations.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230711120916.4165894-4-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-24 16:25:39 +05:30
Dmitry Baryshkov
28e265bf84 phy: qcom-qmp-combo: simplify clock handling 
For the existing PHYs for new binding we are going to drop ref_clk_src
clock and always use ref clock. Rather than introducing additional code
to handle legacy vs current bindings (and clock names), use
devm_clk_bulk_get_optional() when new bindings are used and
devm_clk_bulk_get_all() when legacy bindings are in place.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230711120916.4165894-3-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-24 16:25:39 +05:30
Dmitry Baryshkov
57a79ce964 dt-bindings: phy: migrate combo QMP PHY bindings to qcom,sc8280xp-qmp-usb43dp-phy.yaml 
Migrate legacy bindings (described in qcom,sc7180-qmp-usb3-dp-phy.yaml)
to qcom,sc8280xp-qmp-usb43dp-phy.yaml. This removes a need to declare
the child PHY node or split resource regions.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230711120916.4165894-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-24 16:25:39 +05:30
Yang Li
f5a8ecef3c phy: Remove duplicated include in xusb.c 
./drivers/phy/tegra/xusb.c: linux/platform_device.h is included more than once.

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5930
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20230719003614.5506-1-yang.lee@linux.alibaba.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-24 16:24:19 +05:30
Changhuang Liang
f8aa660841 phy: starfive: Add mipi dphy rx support 
Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to
transfer CSI camera data.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Minda Chen <minda.chen@starfivetech.com>
Link: https://lore.kernel.org/r/20230718070803.16660-3-changhuang.liang@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-24 16:13:03 +05:30
Changhuang Liang
ae07a9a865 dt-bindings: phy: Add starfive,jh7110-dphy-rx 
StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
a M31 IP. Add a binding for it.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230718070803.16660-2-changhuang.liang@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-24 16:13:03 +05:30
Dan Carpenter
86fe3e9f4c phy: starfive: fix error code in probe 
This is using the wrong pointer, "phy->regs" vs "phy->phy".

Fixes: fd097f48ee ("phy: starfive: Add JH7110 PCIE 2.0 PHY driver")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/3cc81f2a-efd7-4ef7-ae6b-e38c91efe153@moroto.mountain
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-24 15:53:54 +05:30
Sebastian Reichel
f66782cff4 dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy 
When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588
support was included, but the DT binding does not reflect this.
This adds the missing bits.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230717173512.65169-2-sebastian.reichel@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-18 11:45:05 +05:30
Mrinmay Sarkar
a05b6d5135 phy: qcom-qmp-pcie: add support for sa8775p 
Add support for dual and four lane PHY found on sa8755p platform.

Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Link: https://lore.kernel.org/r/1689311319-22054-5-git-send-email-quic_msarkar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-18 11:37:10 +05:30
Mrinmay Sarkar
fd2d4e4c19 dt-bindings: phy: qcom,qmp: Add sa8775p QMP PCIe PHY 
Add devicetree YAML binding for Qualcomm QMP PCIe PHY
for SA8775p platform.

Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Link: https://lore.kernel.org/r/1689311319-22054-3-git-send-email-quic_msarkar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-18 11:37:10 +05:30
Rob Herring
7559e7572c phy: Explicitly include correct DT includes 
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for drivers/phy/phy-can-transceiver.c
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-17 11:52:56 +05:30
Andrew Davis
1fdfa7cccd phy: ti: gmii-sel: Allow parent to not be syscon node 
If the parent node is not a syscon type, then fallback and check
if we can get a regmap from our own node. This no longer forces
us to make the parent of this node a syscon node when that might
not be appropriate.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20230713200957.134480-1-afd@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-14 18:24:31 +05:30
Sean Anderson
76009ee76e phy: zynqmp: Allow variation in refclk rate 
Due to limited available frequency ratios, the reference clock rate may
not be exactly the same as the required rate. Allow a small (100 ppm)
deviation.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Link: https://lore.kernel.org/r/20230711194542.898230-1-sean.anderson@seco.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:44 +05:30
Dmitry Baryshkov
20b5c6ae18 phy: qcom-qmp-ufs: populate offsets configuration 
Populate offsets configuration for the rest of UFS PHYs to make it
possible to switch them to the new (single-node) bindings style.

Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230711145153.4167820-3-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:44 +05:30
Dmitry Baryshkov
dc5cb63592 dt-bindings: phy: migrate QMP UFS PHY bindings to qcom,sc8280xp-qmp-ufs-phy.yaml 
Migrate legacy bindings (described in qcom,msm8996-qmp-ufs-phy.yaml)
to qcom,sc8280xp-qmp-ufs-phy.yaml. This removes a need to declare
the child PHY node or split resource regions.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230711145153.4167820-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:44 +05:30
Minda Chen
fd097f48ee phy: starfive: Add JH7110 PCIE 2.0 PHY driver 
Add Starfive JH7110 SoC PCIe 2.0 PHY driver support.
PCIe 2.0 PHY default connect to PCIe controller.
PCIe PHY can connect to USB 3.0 controller.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230629075115.11934-5-minda.chen@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:44 +05:30
Minda Chen
16d3a71c20 phy: starfive: Add JH7110 USB 2.0 PHY driver 
Add Starfive JH7110 SoC USB 2.0 PHY driver support.
USB 2.0 PHY default connect to Cadence USB controller.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230629075115.11934-4-minda.chen@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:44 +05:30
Minda Chen
69d41115b8 dt-bindings: phy: Add StarFive JH7110 PCIe PHY 
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230629075115.11934-3-minda.chen@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:44 +05:30
Minda Chen
2689c9c4ab dt-bindings: phy: Add StarFive JH7110 USB PHY 
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230629075115.11934-2-minda.chen@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:44 +05:30
Marcin Wierzbicki
a1d12987c3 phy: cadence: Sierra: Add single link SGMII register configuration 
Add single link SGMII register configuration for no SSC for
cdns,sierra-phy-t0 compatibility string.
The configuration is based on Sierra Programmer's Guide and
validated in Cisco CrayAR SoC.

Co-developed-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Signed-off-by: Marcin Wierzbicki <mawierzb@cisco.com>
Link: https://lore.kernel.org/r/20230626105533.2999966-1-mawierzb@cisco.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:44 +05:30
Alex Bee
d1ea4239a1 phy/rockchip: inno-hdmi: add more supported pre-pll rates 
This adds a bunch of new pixel clock- and tmds rates to the pre-pll
table which are required to get more VESA and some DMT rates working.

It has been completely re-calculated to match the min- and max-vco of
(750 MHz - 3.2 GHz) requirements. If more than one configuration would
have been possible the lowest fbdiv and refdiv (and therefore lowest
vco rate) has been preferred.

It's important to note, that RK3228 version of the phy does not support
fractional dividers. To support the most possible rates for this version
also in both 8-bit and 10-bit variant, some rates are not exact. The
maximum deviation of the pixel clock is 0.26, which perfectly fits into
VESA DMT recommendation of 0.5%.

I tested all possible rates on several screens from different
manufacturers with both RK3228 and RK3328. Both pre- and post-PLL
locking are slighlty faster now.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20230615171005.2251032-7-jonas@kwiboo.se
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:43 +05:30
Huicong Xu
f79b812baf phy/rockchip: inno-hdmi: force set_rate on power_on 
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and
not in pixel clock rate.
When the hdmiphy clock is configured with the same pixel clock rate using
clk_set_rate() the clock framework do not signal the hdmi phy driver
to set_rate when switching between 8-bit and Deep Color.
This result in pre/post pll not being re-configured when switching between
regular 8-bit and Deep Color video formats.

Fix this by calling set_rate in power_on to force pre pll re-configuration.

Signed-off-by: Huicong Xu <xhc@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20230615171005.2251032-6-jonas@kwiboo.se
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:43 +05:30
Jonas Karlman
19a1d46bd6 phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write 
inno_write is used to configure 0xaa reg, that also hold the
POST_PLL_POWER_DOWN bit.
When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not
taken into consideration.

Fix this by keeping the power down bit until configuration is complete.
Also reorder the reg write order for consistency.

Fixes: 53706a1168 ("phy: add Rockchip Innosilicon hdmi phy")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20230615171005.2251032-5-jonas@kwiboo.se
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:43 +05:30
Jonas Karlman
b001c27d77 phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rate 
no_c is not used in any calculation, lets remove it.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20230615171005.2251032-4-jonas@kwiboo.se
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-07-12 22:27:43 +05:30