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Linus Walleij
0485335295 Merge tag 'samsung-pinctrl-5.15' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel 
Samsung pinctrl drivers changes for v5.15

1. Fix number of pins in one GPIO pin bank.
2. Add support for Exynos850 SoC (Exynos3830).
 2021-08-17 21:58:41 +02:00
Linus Walleij
0dda8b0133 Merge branch 'ib-rockchip' into devel 2021-08-17 01:02:01 +02:00
Jianqun Xu
9ce9a02039 pinctrl/rockchip: drop the gpio related codes 
With the patch to separate the gpio driver from the pinctrl driver, now
the pinctrl-rockchip can drop the gpio related codes now.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210816012146.1119289-1-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-17 01:01:50 +02:00
Jianqun Xu
93103f6eb0 gpio/rockchip: drop irq_gc_lock/irq_gc_unlock for irq set type 
There has spin lock for irq set type already, so drop irq_gc_lock and
irq_gc_unlock.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210816012135.1119234-1-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-17 01:01:50 +02:00
Jianqun Xu
3bcbd1a85b gpio/rockchip: support next version gpio controller 
The next version gpio controller on SoCs like rk3568 have more write
mask bits for registers.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210816012123.1119179-1-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-17 01:01:50 +02:00
Jianqun Xu
ff96a8c21c gpio/rockchip: use struct rockchip_gpio_regs for gpio controller 
Store register offsets in the struct rockchip_gpio_regs, this patch
prepare for the driver update for new gpio controller.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210816012111.1119125-1-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-17 01:01:49 +02:00
Jianqun Xu
936ee2675e gpio/rockchip: add driver for rockchip gpio 
This patch add support for rockchip gpio controller, which is supported
in pinctrl driver in the past.

With this patch, the pinctrl-rockchip driver will drop gpio related
codes and populate platform driver to gpio-rockchip.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210816012053.1119069-1-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-17 01:01:49 +02:00
Jianqun Xu
75d1415ea5 dt-bindings: gpio: change items restriction of clock for rockchip,gpio-bank 
In the past we only need on clock which name "pclk" for a gpio controller.
In the new version gpio controller, there add some register to change
debounce clock dynamic, so the dt node needs to add the second clock, we
call it "dbclk".

The clock property need 2 items on some rockchip chips such as RK3568
SoCs.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210816011948.1118959-5-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-17 01:01:49 +02:00
Jianqun Xu
5f82afd868 pinctrl/rockchip: add pinctrl device to gpio bank struct 
Store a pointer from the pinctrl device for the gpio bank.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210816011948.1118959-4-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-17 01:01:49 +02:00
Jianqun Xu
e1450694e9 pinctrl/rockchip: separate struct rockchip_pin_bank to a head file 
Separate struct rockchip_pin_bank to pinctrl-rockchip.h file, which will
be used by gpio-rockchip driver in the future.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210816011948.1118959-3-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-17 01:01:49 +02:00
Jianqun Xu
4b522bbf80 pinctrl/rockchip: always enable clock for gpio controller 
Since gate and ungate pclk of gpio has very litte benifit for system
power consumption, just keep it always ungate.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210816011948.1118959-2-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-17 01:01:49 +02:00
Linus Walleij
8cd99e3e22 Merge tag 'renesas-pinctrl-for-v5.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel 
pinctrl: renesas: Updates for v5.15 (take two)

  - Add pin control and GPIO support for the new RZ/G2L SoC.
 2021-08-14 00:39:33 +02:00
Lad Prabhakar
c4c4637eb5 pinctrl: renesas: Add RZ/G2L pin and gpio controller driver 
Add support for pin and gpio controller driver for RZ/G2L SoC.

Based on a patch in the BSP by Hien Huynh <hien.huynh.px@renesas.com>.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210727112328.18809-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-08-13 12:09:04 +02:00
Sam Protsenko
cdd3d945dc pinctrl: samsung: Add Exynos850 SoC specific data 
Add Samsung Exynos850 SoC specific data to enable pinctrl support for
all platforms based on Exynos850.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210811114827.27322-3-semen.protsenko@linaro.org
[krzysztof: lower-case the hex-numbers]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
 2021-08-13 09:39:42 +02:00
Sam Protsenko
71b833b329 dt-bindings: pinctrl: samsung: Add Exynos850 doc 
Document compatible string for Exynos850 SoC. Nothing else is changed,
as Exynos850 SoC uses already existing samsung pinctrl driver.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210811114827.27322-2-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
 2021-08-13 09:38:09 +02:00
Shyam Sundar S K
a58b06083f MAINTAINERS: Add maintainers for amd-pinctrl driver 
Adding Basavaraj and myself to the maintainers list for amd-pinctrl
driver.

Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20210812115322.765379-1-Shyam-sundar.S-k@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-12 14:12:58 +02:00
Lakshmi Sowjanya D
ffd4e73935 pinctrl: Add Intel Keem Bay pinctrl driver 
About Intel Keem Bay:
-------------------
Intel Keem Bay is a computer vision AI accelerator SoC based on ARM CPU.
Documentation of Keem Bay: Documentation/vpu/vpu-stack-overview.rst.

Pinctrl IP:
----------
The SoC has a customised pinmux controller IP which controls pin
multiplexing and configuration.

Keem Bay pinctrl IP is not based on and have nothing in common with the
existing pinctrl drivers. The registers used are incompatible with the
existing drivers, so it requires a new driver.

Add pinctrl driver to enable pin control support in the Intel Keem Bay SoC.

Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
Co-developed-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
Reviewed-by: Mark Gross <mgross@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210806142527.29113-3-lakshmi.sowjanya.d@intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 15:13:14 +02:00
Lakshmi Sowjanya D
d2083893e4 dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver 
Add Device Tree bindings documentation for Intel Keem Bay
SoC's pin controller.
Add entry for INTEL Keem Bay pinctrl driver in MAINTAINERS file

Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
Co-developed-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
Acked-by: Mark Gross <mgross@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210806142527.29113-2-lakshmi.sowjanya.d@intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 15:13:14 +02:00
Yang Yingliang
3fb5c90452 pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered device 
It's not necessary to unregister pin controller device registered
with devm_pinctrl_register() and using pinctrl_unregister() leads
to a double free.

Fixes: fa99e70138 ("pinctrl: zynqmp: some code cleanups")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210729071905.3235953-1-yangyingliang@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 15:09:22 +02:00
satya priya
f03f5c75f5 dt-bindings: pinctrl: qcom-pmic-gpio: Remove the interrupts property 
Remove the interrupts property as we no longer specify it.

Signed-off-by: satya priya <skakit@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1627910464-19363-4-git-send-email-skakit@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 13:59:30 +02:00
satya priya
328fb93a84 dt-bindings: pinctrl: qcom-pmic-gpio: Convert qcom pmic gpio bindings to YAML 
Convert Qualcomm PMIC GPIO bindings from .txt to .yaml format.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1627910464-19363-3-git-send-email-skakit@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 13:55:43 +02:00
Chen-Yu Tsai
936c985478 dt-bindings: pinctrl: mt8195: Use real world values for drive-strength arguments 
The original binding submission for MT8195 pinctrl described the
possible drive strength values in micro-amps in its description, but
then proceeded to list register values in its device tree binding
constraints.

However, the macros used with the Mediatek pinctrl bindings directly
specify the drive strength in micro-amps, instead of hardware register
values. The current driver implementation in Linux does convert the
value from micro-amps to hardware register values. This implementation
is also used with MT7622 and MT8183, which use real world values in
their device trees.

Given the above, it was likely an oversight to use the raw register
values in the binding. Correct the values in the binding. Also drop
the description since the binding combined with its parent,
pinctrl/pincfg.yaml, the binding is now self-describing.

Fixes: 7f7663899d ("dt-bindings: pinctrl: mt8195: add pinctrl file and binding document")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210726111941.1447057-1-wenst@chromium.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 11:05:14 +02:00
Linus Walleij
379e28b5b3 Merge branch 'ib-mt8135' into devel 2021-08-11 10:50:07 +02:00
Hsin-Yi Wang
b9ffc18c63 dt-bindings: mediatek: convert pinctrl to yaml 
Convert mt65xx, mt6796, mt7622, mt8183 bindings to yaml.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210804044033.3047296-3-hsinyi@chromium.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 10:49:43 +02:00
Hsin-Yi Wang
4e233326e5 arm: dts: mt8183: Move pinfunc to include/dt-bindings/pinctrl 
Move mt8183-pinfunc.h into include/dt-bindings/pinctrl so that we can
include it in yaml examples.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210804044033.3047296-2-hsinyi@chromium.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 10:49:43 +02:00
Hsin-Yi Wang
3acd5d8b7c arm: dts: mt8135: Move pinfunc to include/dt-bindings/pinctrl 
Move mt8135-pinfunc.h into include/dt-bindings/pinctrl so that we can
include it in yaml examples.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210804044033.3047296-1-hsinyi@chromium.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 10:49:43 +02:00
Paul Cercueil
6626a76ef8 pinctrl: ingenic: Add .max_register in regmap_config 
Compute the max register from the GPIO chip offset and number of GPIO
chips.

This permits to read all registers from debugfs.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20210717174836.14776-3-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 10:24:06 +02:00
Paul Cercueil
7261851e93 pinctrl: ingenic: Fix bias config for X2000(E) 
The ingenic_set_bias() function's "bias" argument is not a
"enum pin_config_param", so its value should not be compared against
values of that enum.

This should fix the bias config not working on the X2000(E) SoCs.

Fixes: 943e0da153 ("pinctrl: Ingenic: Add pinctrl driver for X2000.")
Cc: <stable@vger.kernel.org> # v5.12
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20210717174836.14776-2-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 10:24:06 +02:00
Paul Cercueil
d5e9314039 pinctrl: ingenic: Fix incorrect pull up/down info 
Fix the pull up/down info for both the JZ4760 and JZ4770 SoCs, as the
previous values sometimes contradicted what's written in the programming
manual.

Fixes: b5c23aa465 ("pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs")
Cc: <stable@vger.kernel.org> # v4.12
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20210717174836.14776-1-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 10:24:06 +02:00
周琰杰 (Zhou Yanjie)
2a18211b8c pinctrl: Ingenic: Add pinctrl driver for X2100. 
Add support for probing the pinctrl-ingenic driver on the
X2100 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1627108604-91304-5-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 10:22:18 +02:00
周琰杰 (Zhou Yanjie)
bbd33911cf dt-bindings: pinctrl: Add bindings for Ingenic X2100. 
Add the pinctrl bindings for the X2100 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1627108604-91304-4-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 10:22:18 +02:00
周琰杰 (Zhou Yanjie)
b638e0f18d pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760. 
Add SSI pins support for the JZ4755 SoC and the
JZ4760 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1627108604-91304-3-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 10:22:17 +02:00
周琰杰 (Zhou Yanjie)
28c1caaf49 pinctrl: Ingenic: Improve the code. 
1.Rename the original "dmicx" ABIs to "dmic-ifx", since these devices
  have only one DMIC module which has multiple input interfaces. The
  original naming is easy to make users mistakenly think that the
  device has multiple dmic modules. Currently, in the mainline, no
  other devicetree out there is using the "sfc" ABI, so we should be
  able to replace it safely.
2.Rename the original "ssix-ce0" ABIs to "ssix-ce", since the X2000
  have only one ce pin. The original naming is easy to make users
  mistakenly think that the device has multiple ce pins. Currently,
  in the mainline, no other devicetree out there is using the
  "ssix-ce0" ABIs, so we should be able to replace it safely.
3.Split the original "sfc" ABI into "sfc-data", "sfc-ce", "sfc-clk"
  to increase the flexibility when configuring the pins. Currently,
  in the mainline, no other devicetree out there is using the "sfc"
  ABI, so we should be able to replace it safely.
4.There is more than one compatible string in the match table, so
  renaming "ingenic_xxxx_of_match[]" to "ingenic_xxxx_of_matches"
  is more reasonable, and remove the unnecessary commas in
  "ingenic_gpio_of_matches[]" to reduce code size as much as possible.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1627108604-91304-2-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-11 10:22:17 +02:00
Randy Dunlap
5fa9d19b3f pinctrl: aspeed: placate kernel-doc warnings 
Eliminate kernel-doc warnings in drivers/pinctrl/aspeed by using
proper kernel-doc notation.

Fixes these kernel-doc warnings:

drivers/pinctrl/aspeed/pinmux-aspeed.c:61: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
    * Query the enabled or disabled state for a mux function's signal on a pin
drivers/pinctrl/aspeed/pinctrl-aspeed.c:135: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
    * Search for the signal expression needed to enable the pin's signal for the

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: kernel test robot <lkp@intel.com>
Cc: Aditya Srivastava <yashsri421@gmail.com>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: linux-aspeed@lists.ozlabs.org
Cc: openbmc@lists.ozlabs.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20210723034840.8752-1-rdunlap@infradead.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-10 15:29:44 +02:00
Marc Zyngier
1b73e588f4 pinctrl: stmfx: Fix hazardous u8[] to unsigned long cast 
Casting a small array of u8 to an unsigned long is *never* OK:

- it does funny thing when the array size is less than that of a long,
  as it accesses random places in the stack
- it makes everything even more fun with a BE kernel

Fix this by building the unsigned long used as a bitmap byte by byte,
in a way that works across endianess and has no undefined behaviours.

An extra BUILD_BUG_ON() catches the unlikely case where the array
would be larger than a single unsigned long.

Fixes: 1490d9f841 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver")
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Cc: Amelie Delaunay <amelie.delaunay@foss.st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Link: https://lore.kernel.org/r/20210725180830.250218-1-maz@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-10 14:47:59 +02:00
Alexandre Torgue
a022135a19 pinctrl: stm32: Add STM32MP135 SoC support 
STM32MP135 SoC embeds 9 GPIO banks of 16 gpios each. Those GPIO
banks contain same features as STM32MP157 GPIO banks except that
each GPIO line of the STM32MP135 can be secured.

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Arnd Bergmann <arnd@arndb.de
Link: https://lore.kernel.org/r/20210723132810.25728-3-alexandre.torgue@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-10 14:45:27 +02:00
Alexandre Torgue
510fc3487b dt-bindings: pinctrl: stm32: add new compatible for STM32MP135 SoC 
New compatible to manage ball out and pin muxing of STM32MP135 SoC.

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de
Link: https://lore.kernel.org/r/20210723132810.25728-2-alexandre.torgue@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-10 14:44:46 +02:00
Zhen Lei
2ac48d0d48 pinctrl: single: Move test PCS_HAS_PINCONF in pcs_parse_bits_in_pinctrl_entry() to the beginning 
The value of pcs->flags is not overwritten in function
pcs_parse_bits_in_pinctrl_entry() and its subfunctions, so moving this
check to the beginning of the function eliminates unnecessary rollback
operations.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20210722033930.4034-3-thunder.leizhen@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-10 14:42:56 +02:00
Zhen Lei
d789a490d3 pinctrl: single: Fix error return code in pcs_parse_bits_in_pinctrl_entry() 
Fix to return -ENOTSUPP instead of 0 when PCS_HAS_PINCONF is true, which
is the same as that returned in pcs_parse_pinconf().

Fixes: 4e7e8017a8 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20210722033930.4034-2-thunder.leizhen@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-10 14:42:55 +02:00
Bjorn Andersson
182700f258 pinctrl: qcom: spmi-gpio: Add pmc8180 & pmc8180c 
The SC8180x platform comes with PMC8180 and PMC8180c, add support for
the GPIO controller in these PMICs.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210629003851.1787673-1-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-08-10 14:37:36 +02:00
Lad Prabhakar
7958f88aa6 dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl 
Add device tree binding documentation and header file for Renesas
RZ/G2L pinctrl.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210727112328.18809-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-08-10 13:12:50 +02:00
Jaehyoung Choi
70115558ab pinctrl: samsung: Fix pinctrl bank pin count 
Commit 1abd18d1a5 ("pinctrl: samsung: Register pinctrl before GPIO")
changes the order of GPIO and pinctrl registration: now pinctrl is
registered before GPIO. That means gpio_chip->ngpio is not set when
samsung_pinctrl_register() called, and one cannot rely on that value
anymore. Use `pin_bank->nr_pins' instead of `pin_bank->gpio_chip.ngpio'
to fix mentioned inconsistency.

Fixes: 1abd18d1a5 ("pinctrl: samsung: Register pinctrl before GPIO")
Signed-off-by: Jaehyoung Choi <jkkkkk.choi@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210730192905.7173-1-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
 2021-08-02 15:22:18 +02:00
Iskren Chernev
4b77f1dff5 drivers: qcom: pinctrl: Add pinctrl driver for sm6115 
Based on CAF implementation with egpio/wake_reg support removed.

Similar function names were merged to reduce total number of functions.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210723192352.546902-3-iskren.chernev@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-07-31 23:23:06 +02:00
Iskren Chernev
d1945f6c5b dt-bindings: pinctrl: qcom: Add SM6115 pinctrl bindings 
Add device tree binding Documentation details for Qualcomm SM6115 and
SM4250 pinctrl.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210723192352.546902-2-iskren.chernev@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-07-31 23:22:59 +02:00
Linus Walleij
d7eb35beda Merge tag 'renesas-pinctrl-for-v5.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel 
pinctrl: renesas: Updates for v5.15

  - Add bias support for the R-Car D3 SoC,
  - Miscellaneous fixes and improvements.
 2021-07-30 16:11:37 +02:00
Sai Krishna Potthuri
cdd5732554 pinctrl: pinctrl-zynq: Add support for 'power-source' parameter 
Add support for generic pin parameter 'power-source'.
To maintain the backward compatibility, 'io-standard' parameter is still
supported in the driver.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1626868353-96475-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-07-30 14:40:42 +02:00
Sai Krishna Potthuri
ef641c449e dt-bindings: pinctrl-zynq: Replace 'io-standard' with 'power-source' 
Replace custom pin configuration option 'io-standard' with generic property
'power-source' for Zynq pinctrl also add dt-binding file contains pin
configuration defines for Zynq pinctrl.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1626868353-96475-3-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-07-30 14:40:33 +02:00
Sai Krishna Potthuri
153df45acd dt-bindings: pinctrl: pinctrl-zynq: Convert to yaml 
Convert the Zynq pinctrl binding file to yaml.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1626868353-96475-2-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-07-30 14:40:23 +02:00
Jiaxun Yang
6ceb3c6406 pinctrl: pistachio: Make it as an option 
So it will be avilable for generic MIPS kernel.

--

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
v3: Depend on OF as well
Link: https://lore.kernel.org/r/20210721030134.10562-7-jiaxun.yang@flygoat.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-07-30 14:37:36 +02:00
Fabio Estevam
2fefcf2400 pinctrl: imx8dxl: Constify imx_pinctrl_soc_info 
The imx_pinctrl_soc_info structure content is never changed, so it can be
declared as 'const', like it is done on all other i.MX pinctrl drivers.

Make it 'const' in this driver too.

Reported-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20210716131341.3370620-1-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-07-30 12:06:02 +02:00