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Author SHA1 Message Date
Likun Gao
02bb391d91 drm/amd/powerplay: make gfx ds can be configure for sienna_cichlid 
Make GFX deep sleep can be configure for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:10 -04:00
Likun Gao
65297d5017 drm/amdgpu/powerplay: set UCLK DPM for sienna_cichlid 
Enable uclk dpm for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:09 -04:00
Likun Gao
094cdf15e9 drm/amdgpu/powerplay: set Thermal control for sienna_cichlid 
Enable Auto Thermal Throttling for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:09 -04:00
Likun Gao
983ab9f284 drm/amd/powerplay: enable SOC Clock Deep Sleep for sienna_cichlid 
Enable System On Chip Clock Deep Sleep for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:08 -04:00
Likun Gao
15dbe18fa6 drm/amd/powerplay: enable Graphics Clock Deep Sleep for sienna_cichlid 
Enable Graphics Clock Deep Sleep for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:08 -04:00
Likun Gao
62c1ea6bba drm/amd/powerplay: enable Ultra Low Voltage for sienna_cichlid 
Support Ultra Low Voltage for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:07 -04:00
Likun Gao
4cd4f45b65 drm/amd/powerplay: set FCLK DPM for sienna_cichlid 
Support for FCLK DPM for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:07 -04:00
Likun Gao
fea905d471 drm/amd/powerplay: set SOCCLK DPM for sienna_cichlid 
Support for SOCCLK DPM for sienna_cichlid.
Use feature mask to control DPM for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:06 -04:00
Likun Gao
9ad9c8acc8 drm/amd/powerplay: add support to set performance level for sienna_cichlid 
Support for performance level set for sienna_cichlid.
Set standard performance level not fully support, will set to auto
performance level.
Set peak performance level not fully support, will do nothing with it.
Force clk level only support for 2 level for fine grained DPM.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:06 -04:00
Likun Gao
b455159c05 drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2) 
SMU11 based similar to navi1x.

v2: squash in SMU IF updates

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:05 -04:00
Likun Gao
9a98676007 drm/amdgpu: add virtual display support for sienna_cichlid 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:05 -04:00
Likun Gao
58139a42dc drm/amdgpu/gfx10: change register configure for sienna_cichlid 
Update sienna_cichlid register configuration for sienna_cichlid
to match the update of header files.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:05 -04:00
Likun Gao
d682a353f3 drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:04 -04:00
Likun Gao
157e72e831 drm/amdgpu: add sdma ip block for sienna_cichlid (v5) 
Sienna_Cichlid have 4 sdma controllers.

v2: add missing license to sdma_common.h (Alex)
v3: rebase (Alex)
v4: squash in policy fix (Alex)
v4: squash in fw_name fix

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:04 -04:00
Likun Gao
06ff634c0d drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2) 
Add irq src headers for additional SDMA blocks.

v2: Add missing licenses (Alex)

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:03 -04:00
Likun Gao
933c8a93e2 drm/amdgpu: add gfx ip block for sienna_cichlid (v3) 
Add support for GC 10.3.

v2: Squash in gb_addr_config fix (Alex)
v3: Add num_pkrs support (Alex)

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:03 -04:00
Likun Gao
757b3af8ec drm/amdgpu: add ih ip block for sienna_cichlid 
Update IH handling for sienna_cichlid

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:02 -04:00
Likun Gao
0b3df16b5a drm/amdgpu: add gmc ip block for sienna_cichlid 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:02 -04:00
Likun Gao
af01d47d3c drm/amdgpu: add support gfxhub for sienna_cichlid (v3) 
GFX10.3 is used for sienna_cichlid.

v2: squash in BANK_SELECT and FRAGMENT_SIZE fixes (Alex)
v3: squash in smallk update (Alex)

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:01 -04:00
Likun Gao
ffffb96d11 drm/amdgpu: add support on mmhub for sienna_cichlid 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:01 -04:00
Likun Gao
2e1ba10e92 drm/amdgpu/soc15: add common ip block for sienna_cichlid 
Add common ip block for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:00 -04:00
Likun Gao
dccdbf3f96 drm/amdgpu: initialize IP offset for sienna_cichlid (v2) 
Add IP offset headers and state.

V2: squash in updates (Alex)

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:00 -04:00
Likun Gao
117910ed92 drm/amdgpu/soc15: add support for sienna_cichlid 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:59 -04:00
Likun Gao
2f7f522722 drm/amdgpu/gfx10: add clockgating support for sienna_cichlid 
Same as navi10.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:59 -04:00
Likun Gao
57d706026f drm/amdgpu/gmc10: add sienna_cichlid support 
Same as navi10.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:58 -04:00
Likun Gao
6c06333073 drm/amdgpu/gfx10: add support for sienna_cichlid firmware 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:58 -04:00
Likun Gao
11e8aef52e drm/amdgpu: set asic family and ip blocks for sienna_cichlid 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:57 -04:00
Likun Gao
d4f3c3905b drm/amdgpu: set fw load type for sienna_cichlid 
Same as Navi1x.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:57 -04:00
Likun Gao
c0a43457dc drm/amdgpu: add sienna_cichlid gpu info firmware v2 
gpu info fw contains chip specific parameters.

v2: fix fw_name

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:57 -04:00
Likun Gao
ccaf72d3c2 drm/amdgpu: add sienna_cichlid asic type 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:56 -04:00
Jerry (Fangzhi) Zuo
241b2ec931 drm/amd/display: Add dcn30 Headers (v2) 
DCN 3.0 display controller registers

v2: squash in updates from Bhawan.

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:56 -04:00
Leo Liu
a5a2597771 drm/amdgpu: add VCN3.0 register headers (v2) 
Sienna_Cichlid VCN headers

v2: squash in updates (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:55 -04:00
Yong Zhao
e54294d665 drm/amdgpu: Add ATHUB 2.1 header files (v2) 
v2: squash in updates (Alex)

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:55 -04:00
Likun Gao
b4ebd8717e drm/amdgpu: add GC 10.3 header files (v2) 
Add GC10.3 related header files.

v2: squash in updates (Alex)

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:54 -04:00
Rajneesh Bhardwaj
8b80d74bdb drm/amdgpu: restrict bo mapping within gpu address limits 
Have strict check on bo mapping since on some systems, such as A+A or
hybrid, the cpu might support 5 level paging or can address memory above
48 bits but gpu might be limited by hardware to just use 48 bits. In
general, this applies to all asics where this limitation can be checked
against their max_pfn range. This restricts the range to map bo within
pratical limits of cpu and gpu for shared virtual memory access.

Reviewed-by: Oak Zeng <oak.zeng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:38 -04:00
Kent Russell
81a1624111 drm/amdgpu: Add unique_id and serial_number for Arcturus v3 
Add support for unique_id and serial_number, as these are now
the same value, and will be for future ASICs as well.

v2: Explicitly create unique_id only for VG10/20/ARC
v3: Change set_unique_id to get_unique_id for clarity

Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-02 16:47:58 -04:00
Kent Russell
bce9ff0eac drm/amdgpu: Add ReadSerial defines for Arcturus 
Add the ReadSerial definitions for Arcturus to the arcturus_ppsmc.h
header for use with unique_id

Unrevert: Supported in SMU 54.23, update values to match SMU spec

Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-02 16:47:49 -04:00
Guchun Chen
9e69b1ee1d drm/amdgpu: remove useless code in RAS 
Module parameter amdgpu_ras_mask has been involved in
the calculation of ras support capability, so drop this
redundant code.

Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-02 16:47:43 -04:00
Guchun Chen
5e91160ac0 drm/amdgpu: fix RAS memory leak in error case 
RAS context memory needs to freed in failure case.

Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-02 16:47:20 -04:00
Alex Deucher
d43f7ff69c drm/amdgpu/fru: fix header guard and include header 
Fix the fru eeprom header guard and include it in the .c file.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-05-29 13:55:08 -04:00
Alex Deucher
3967ae6d79 drm/amdgpu/nv: enable init reset check 
gpu reset is implemented for navi so we can enable this.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-05-29 13:55:08 -04:00
Alex Deucher
337b72444e drm/amdgpu/nv: remove some dead code 
navi never supported the pci config reset.  Neither did
vega.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-05-29 13:55:07 -04:00
Alex Deucher
007026cd73 drm/amdgpu/nv: allow access to SDMA status registers 
For access via ioctl for tools like umr and mesa.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-05-29 13:55:07 -04:00
Alex Deucher
c1cf79ca5c drm/amdgpu: use IP discovery table for renoir 
Rather than relying on gpu info firmware.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-05-29 13:55:07 -04:00
Alex Deucher
4292b0b202 drm/amdgpu: clean up discovery testing 
Rather than checking of the variable is enabled and the
chip is the right family check for the presence of the
discovery table.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-05-29 13:55:07 -04:00
Alex Deucher
258620d0b3 drm/amdgpu: skip gpu_info firmware if discovery info is available 
The GPU info firmware is only applicable at bring up when the
IP discovery table is not present.  If it's available, use that
first and then fallback to parsing the gpu info firmware.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-05-29 13:55:07 -04:00
Evan Quan
22f1e0e8e4 drm/amd/powerplay: give better names for the thermal IRQ related APIs 
Thermal control is performed by PMFW. What handled in driver is
just whether or not to enable the alert(to driver).

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-05-29 13:55:07 -04:00
Evan Quan
be80b431fa drm/amd/powerplay: use the common APIs for IRQ disablement/enablement 
Also the new logics for MP1 SW IRQs disablement/enablement are added.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-05-29 13:55:07 -04:00
Evan Quan
4f1fad0e9d drm/amd/powerplay: stop thermal IRQs on suspend 
Added missing thermal IRQs disablement on suspend.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-05-29 13:55:07 -04:00
Evan Quan
b265bdbd9f drm/amdgpu: added a sysfs interface for thermal throttling related V4 
User can check and set the enablement of throttling logging and
the interval between each logging.

V2: simplify the sysfs interface(no string parsing)
V3: add proper lock protection on updating throttling_logging_rs.interval
V4: documentation cosmetic per Luben's suggestion

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-05-29 13:55:07 -04:00