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ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase properties

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dtschema/schemas/bootph.yaml describe various node usage during
boot phases with DT.

TQMa6UL need eMMC, I2C, GPIO and QSPI access during boot process.

Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Max Merchel
2026-02-20 15:31:03 +01:00
committed by Frank Li
parent 72d47f32fd
commit feb90561be
7 changed files with 16 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi
View File

@@ -26,6 +26,7 @@ &i2c4 {
pinctrl-1 = <&pinctrl_i2c4_recovery>;
scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
bootph-pre-ram;
status = "okay";
pfuze3000: pmic@8 {
@@ -140,9 +141,14 @@ rtc0: rtc@68 {
};
};
&gpio1 {
bootph-pre-ram;
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
bootph-pre-ram;
/*
* PMIC & temperature sensor IRQ
@@ -159,6 +165,7 @@ pmic-int-hog {
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
bootph-pre-ram;
status = "okay";
flash0: flash@0 {
@@ -168,6 +175,7 @@ flash0: flash@0 {
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
vcc-supply = <&reg_vldo4>;
bootph-pre-ram;
partitions {
compatible = "fixed-partitions";
@@ -189,6 +197,7 @@ &usdhc2 {
non-removable;
no-sdio;
no-sd;
bootph-all;
status = "okay";
};
@@ -212,5 +221,6 @@ pinctrl_pmic: pmicgrp {
/* PMIC irq */
MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099
>;
bootph-pre-ram;
};
};

1
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi
View File

@@ -33,6 +33,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
/* rst */
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
>;
bootph-all;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

1
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi
View File

@@ -33,6 +33,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
/* rst */
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
>;
bootph-all;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

1
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi
View File

@@ -39,5 +39,6 @@ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
bootph-pre-ram;
};
};

1
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi
View File

@@ -44,5 +44,6 @@ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
bootph-pre-ram;
};
};

1
arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi
View File

@@ -38,6 +38,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
/* rst */
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
>;
bootph-all;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

1
arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi
View File

@@ -38,6 +38,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
/* rst */
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
>;
bootph-all;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {