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spi: Use FIELD_MODIFY() for bitfield operations

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Hans Zhang <18255117159@163.com> says:

Replace open-coded bitfield modifications with the standard FIELD_MODIFY()
macro across multiple SPI controller drivers. This improves readability and
adds compile-time checking without functional changes.

Each patch modifies a single driver, allowing independent review and
application.

Link: https://patch.msgid.link/20260430155456.36998-1-18255117159@163.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Mark Brown
2026-05-11 21:05:13 +09:00
parent ca15b1d15b ce7984bea2
commit fe46080cc0
10 changed files with 27 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/spi/spi-amlogic-spifc-a1.c
View File

@@ -206,10 +206,9 @@ static int amlogic_spifc_a1_read(struct amlogic_spifc_a1 *spifc, void *buf,
u32 val = readl(spifc->base + SPIFC_A1_USER_CTRL3_REG);
int ret;
val &= ~(SPIFC_A1_USER_DIN_MODE | SPIFC_A1_USER_DIN_BYTES);
val |= SPIFC_A1_USER_DIN_ENABLE;
val |= FIELD_PREP(SPIFC_A1_USER_DIN_MODE, mode);
val |= FIELD_PREP(SPIFC_A1_USER_DIN_BYTES, size);
FIELD_MODIFY(SPIFC_A1_USER_DIN_MODE, &val, mode);
FIELD_MODIFY(SPIFC_A1_USER_DIN_BYTES, &val, size);
writel(val, spifc->base + SPIFC_A1_USER_CTRL3_REG);
ret = amlogic_spifc_a1_request(spifc, true);

13
drivers/spi/spi-amlogic-spisg.c
View File

@@ -600,14 +600,11 @@ static int aml_spisg_prepare_message(struct spi_controller *ctlr,
spisg->bytes_per_word = spi->bits_per_word >> 3;
spisg->cfg_spi &= ~CFG_SLAVE_SELECT;
spisg->cfg_spi |= FIELD_PREP(CFG_SLAVE_SELECT, spi_get_chipselect(spi, 0));
spisg->cfg_bus &= ~(CFG_CPOL | CFG_CPHA | CFG_B_L_ENDIAN | CFG_HALF_DUPLEX);
spisg->cfg_bus |= FIELD_PREP(CFG_CPOL, !!(spi->mode & SPI_CPOL)) |
FIELD_PREP(CFG_CPHA, !!(spi->mode & SPI_CPHA)) |
FIELD_PREP(CFG_B_L_ENDIAN, !!(spi->mode & SPI_LSB_FIRST)) |
FIELD_PREP(CFG_HALF_DUPLEX, !!(spi->mode & SPI_3WIRE));
FIELD_MODIFY(CFG_SLAVE_SELECT, &spisg->cfg_spi, spi_get_chipselect(spi, 0));
FIELD_MODIFY(CFG_CPOL, &spisg->cfg_bus, !!(spi->mode & SPI_CPOL));
FIELD_MODIFY(CFG_CPHA, &spisg->cfg_bus, !!(spi->mode & SPI_CPHA));
FIELD_MODIFY(CFG_B_L_ENDIAN, &spisg->cfg_bus, !!(spi->mode & SPI_LSB_FIRST));
FIELD_MODIFY(CFG_HALF_DUPLEX, &spisg->cfg_bus, !!(spi->mode & SPI_3WIRE));
return 0;
}

3
drivers/spi/spi-cadence-xspi.c
View File

@@ -453,8 +453,7 @@ static bool cdns_mrvl_xspi_setup_clock(struct cdns_xspi_dev *cdns_xspi,
writel(clk_reg,
cdns_xspi->auxbase + MRVL_XSPI_CLK_CTRL_AUX_REG);
clk_reg = FIELD_PREP(MRVL_XSPI_CLK_DIV, i);
clk_reg &= ~MRVL_XSPI_CLK_DIV;
clk_reg |= FIELD_PREP(MRVL_XSPI_CLK_DIV, i);
FIELD_MODIFY(MRVL_XSPI_CLK_DIV, &clk_reg, i);
clk_reg |= MRVL_XSPI_CLK_ENABLE;
clk_reg |= MRVL_XSPI_IRQ_ENABLE;
update_clk = true;

5
drivers/spi/spi-meson-spicc.c
View File

@@ -539,9 +539,8 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
/* Setup word width */
conf &= ~SPICC_BITLENGTH_MASK;
conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
(spicc->bytes_per_word << 3) - 1);
FIELD_MODIFY(SPICC_BITLENGTH_MASK, &conf,
(spicc->bytes_per_word << 3) - 1);
/* Ignore if unchanged */
if (conf != conf_orig)

12
drivers/spi/spi-nxp-xspi.c
View File

@@ -493,9 +493,8 @@ static void nxp_xspi_disable_ddr(struct nxp_xspi *xspi)
writel(reg, base + XSPI_MCR);
reg &= ~XSPI_MCR_DDR_EN;
reg &= ~XSPI_MCR_DQS_FA_SEL_MASK;
/* Use dummy pad loopback mode to sample data */
reg |= FIELD_PREP(XSPI_MCR_DQS_FA_SEL_MASK, 0x01);
FIELD_MODIFY(XSPI_MCR_DQS_FA_SEL_MASK, &reg, 0x01);
writel(reg, base + XSPI_MCR);
xspi->support_max_rate = 133000000;
@@ -524,15 +523,13 @@ static void nxp_xspi_enable_ddr(struct nxp_xspi *xspi)
writel(reg, base + XSPI_MCR);
reg |= XSPI_MCR_DDR_EN;
reg &= ~XSPI_MCR_DQS_FA_SEL_MASK;
/* Use external dqs to sample data */
reg |= FIELD_PREP(XSPI_MCR_DQS_FA_SEL_MASK, 0x03);
FIELD_MODIFY(XSPI_MCR_DQS_FA_SEL_MASK, &reg, 0x03);
writel(reg, base + XSPI_MCR);
xspi->support_max_rate = 200000000;
reg = readl(base + XSPI_FLSHCR);
reg &= ~XSPI_FLSHCR_TDH_MASK;
reg |= FIELD_PREP(XSPI_FLSHCR_TDH_MASK, 0x01);
FIELD_MODIFY(XSPI_FLSHCR_TDH_MASK, &reg, 0x01);
writel(reg, base + XSPI_FLSHCR);
reg = FIELD_PREP(XSPI_SMPR_DLLFSMPFA_MASK, 0x04);
@@ -1096,8 +1093,7 @@ static int nxp_xspi_default_setup(struct nxp_xspi *xspi)
/* Give read/write access right to EENV0 */
reg = readl(base + XSPI_FRAD0_WORD2);
reg &= ~XSPI_FRAD0_WORD2_MD0ACP_MASK;
reg |= FIELD_PREP(XSPI_FRAD0_WORD2_MD0ACP_MASK, 0x03);
FIELD_MODIFY(XSPI_FRAD0_WORD2_MD0ACP_MASK, &reg, 0x03);
writel(reg, base + XSPI_FRAD0_WORD2);
/* Enable the FRAD check for EENV0 */

5
drivers/spi/spi-sn-f-ospi.c
View File

@@ -222,9 +222,8 @@ static void f_ospi_config_clk(struct f_ospi *ospi, u32 device_hz)
*/
val = readl(ospi->base + OSPI_CLK_CTL);
val &= ~(OSPI_CLK_CTL_PHA | OSPI_CLK_CTL_DIV);
val |= FIELD_PREP(OSPI_CLK_CTL_PHA, OSPI_CLK_CTL_PHA_180)
| FIELD_PREP(OSPI_CLK_CTL_DIV, div_reg);
FIELD_MODIFY(OSPI_CLK_CTL_PHA, &val, OSPI_CLK_CTL_PHA_180);
FIELD_MODIFY(OSPI_CLK_CTL_DIV, &val, div_reg);
writel(val, ospi->base + OSPI_CLK_CTL);
}

7
drivers/spi/spi-stm32-ospi.c
View File

@@ -470,10 +470,9 @@ static int stm32_ospi_send(struct spi_device *spi, const struct spi_mem_op *op)
u8 cs = spi->chip_select[ffs(spi->cs_index_mask) - 1];
cr = readl_relaxed(ospi->regs_base + OSPI_CR);
cr &= ~CR_CSSEL;
cr |= FIELD_PREP(CR_CSSEL, cs);
cr &= ~CR_FMODE_MASK;
cr |= FIELD_PREP(CR_FMODE_MASK, ospi->fmode);
FIELD_MODIFY(CR_CSSEL, &cr, cs);
FIELD_MODIFY(CR_FMODE_MASK, &cr, ospi->fmode);
writel_relaxed(cr, regs_base + OSPI_CR);
if (op->data.nbytes)

5
drivers/spi/spi-stm32-qspi.c
View File

@@ -374,9 +374,8 @@ static int stm32_qspi_send(struct spi_device *spi, const struct spi_mem_op *op)
int timeout, err = 0, err_poll_status = 0;
cr = readl_relaxed(qspi->io_base + QSPI_CR);
cr &= ~CR_PRESC_MASK & ~CR_FSEL;
cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
cr |= FIELD_PREP(CR_FSEL, flash->cs);
FIELD_MODIFY(CR_PRESC_MASK, &cr, flash->presc);
FIELD_MODIFY(CR_FSEL, &cr, flash->cs);
writel_relaxed(cr, qspi->io_base + QSPI_CR);
if (op->data.nbytes)

3
drivers/spi/spi-sunplus-sp7021.c
View File

@@ -290,8 +290,7 @@ static void sp7021_spi_setup_clk(struct spi_controller *ctlr, struct spi_transfe
div = max(2U, clk_rate / xfer->speed_hz);
clk_sel = (div / 2) - 1;
pspim->xfer_conf &= ~SP7021_CLK_MASK;
pspim->xfer_conf |= FIELD_PREP(SP7021_CLK_MASK, clk_sel);
FIELD_MODIFY(SP7021_CLK_MASK, &pspim->xfer_conf, clk_sel);
writel(pspim->xfer_conf, pspim->m_base + SP7021_SPI_CONFIG_REG);
}

13
drivers/spi/spi-uniphier.c
View File

@@ -184,14 +184,12 @@ static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size)
u32 val;
val = readl(priv->base + SSI_TXWDS);
val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
FIELD_MODIFY(SSI_TXWDS_WDLEN_MASK, &val, size);
FIELD_MODIFY(SSI_TXWDS_DTLEN_MASK, &val, size);
writel(val, priv->base + SSI_TXWDS);
val = readl(priv->base + SSI_RXWDS);
val &= ~SSI_RXWDS_DTLEN_MASK;
val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
FIELD_MODIFY(SSI_RXWDS_DTLEN_MASK, &val, size);
writel(val, priv->base + SSI_RXWDS);
}
@@ -308,9 +306,8 @@ static void uniphier_spi_set_fifo_threshold(struct uniphier_spi_priv *priv,
u32 val;
val = readl(priv->base + SSI_FC);
val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
val |= FIELD_PREP(SSI_FC_TXFTH_MASK, SSI_FIFO_DEPTH - threshold);
val |= FIELD_PREP(SSI_FC_RXFTH_MASK, threshold);
FIELD_MODIFY(SSI_FC_TXFTH_MASK, &val, SSI_FIFO_DEPTH - threshold);
FIELD_MODIFY(SSI_FC_RXFTH_MASK, &val, threshold);
writel(val, priv->base + SSI_FC);
}