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arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS

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As per the GXM datasheet add missing cache information to the Amlogic GXM
SoC.

- Each Cortex-A53 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-6-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This commit is contained in:
Anand Moon
2025-08-25 12:21:45 +05:30
committed by Neil Armstrong
parent 3b6ad2a433
commit fe2c12bc0a
1 changed files with 24 additions and 0 deletions
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24
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
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@@ -64,6 +64,12 @@ cpu4: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@@ -75,6 +81,12 @@ cpu5: cpu@101 {
reg = <0x0 0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@@ -86,6 +98,12 @@ cpu6: cpu@102 {
reg = <0x0 0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@@ -97,6 +115,12 @@ cpu7: cpu@103 {
reg = <0x0 0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;