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arm64: dts: mediatek: mt7988: Add pcie nodes
Add pcie controllers for mt7988. Reuse mt7986 compatible. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241217091238.16032-11-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Frank Wunderlich
committed by
AngeloGioacchino Del Regno
AngeloGioacchino Del Regno
parent
f693e6ba55
commit
fda61ffb3a
@@ -373,6 +373,158 @@ mmc0: mmc@11230000 {
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status = "disabled";
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};
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pcie@11280000 {
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compatible = "mediatek,mt7986-pcie",
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"mediatek,mt8192-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0 0x11280000 0 0x2000>;
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reg-names = "pcie-mac";
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linux,pci-domain = <3>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x81000000 0x00 0x20000000 0x00
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0x20000000 0x00 0x00200000>,
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<0x82000000 0x00 0x20200000 0x00
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0x20200000 0x00 0x07e00000>;
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clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
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<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
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<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
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<&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2_pins>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc2 0>,
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<0 0 0 2 &pcie_intc2 1>,
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<0 0 0 3 &pcie_intc2 2>,
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<0 0 0 4 &pcie_intc2 3>;
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pcie_intc2: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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pcie@11290000 {
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compatible = "mediatek,mt7986-pcie",
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"mediatek,mt8192-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0 0x11290000 0 0x2000>;
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reg-names = "pcie-mac";
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linux,pci-domain = <2>;
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interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x81000000 0x00 0x28000000 0x00
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0x28000000 0x00 0x00200000>,
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<0x82000000 0x00 0x28200000 0x00
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0x28200000 0x00 0x07e00000>;
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clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
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<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
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<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
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<&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie3_pins>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc3 0>,
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<0 0 0 2 &pcie_intc3 1>,
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<0 0 0 3 &pcie_intc3 2>,
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<0 0 0 4 &pcie_intc3 3>;
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pcie_intc3: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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pcie@11300000 {
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compatible = "mediatek,mt7986-pcie",
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"mediatek,mt8192-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0 0x11300000 0 0x2000>;
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reg-names = "pcie-mac";
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linux,pci-domain = <0>;
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x81000000 0x00 0x30000000 0x00
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0x30000000 0x00 0x00200000>,
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<0x82000000 0x00 0x30200000 0x00
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0x30200000 0x00 0x07e00000>;
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clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
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<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
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<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
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<&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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pcie@11310000 {
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compatible = "mediatek,mt7986-pcie",
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"mediatek,mt8192-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0 0x11310000 0 0x2000>;
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reg-names = "pcie-mac";
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linux,pci-domain = <1>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x81000000 0x00 0x38000000 0x00
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0x38000000 0x00 0x00200000>,
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<0x82000000 0x00 0x38200000 0x00
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0x38200000 0x00 0x07e00000>;
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clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
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<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
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<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
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<&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_pins>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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t-phy@11c50000 {
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compatible = "mediatek,mt7986-tphy",
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"mediatek,generic-tphy-v2";
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