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drm/amdgpu: cleanup dce_virtual
Remove obsolete functions and variables from dce_virtual. Signed-off-by: Ryan Taylor <Ryan.Taylor@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ryan Taylor
committed by
Alex Deucher
Alex Deucher
parent
84ec374bd5
commit
fd922f7a0e
@@ -21,15 +21,9 @@
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*
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*/
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#include <drm/drm_vblank.h>
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#include <drm/drm_atomic_helper.h>
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#include "amdgpu.h"
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#include "amdgpu_pm.h"
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#include "amdgpu_i2c.h"
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#include "atom.h"
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#include "amdgpu_pll.h"
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#include "amdgpu_connectors.h"
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#ifdef CONFIG_DRM_AMDGPU_SI
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#include "dce_v6_0.h"
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#endif
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@@ -43,339 +37,6 @@
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#include "amdgpu_display.h"
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#include "amdgpu_vkms.h"
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#define DCE_VIRTUAL_VBLANK_PERIOD 16666666
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static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
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static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
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static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
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int index);
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static int dce_virtual_pageflip(struct amdgpu_device *adev,
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unsigned crtc_id);
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static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer);
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static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
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int crtc,
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enum amdgpu_interrupt_state state);
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static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
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{
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return 0;
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}
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static void dce_virtual_page_flip(struct amdgpu_device *adev,
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int crtc_id, u64 crtc_base, bool async)
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{
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return;
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}
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static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
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u32 *vbl, u32 *position)
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{
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*vbl = 0;
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*position = 0;
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return -EINVAL;
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}
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static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
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enum amdgpu_hpd_id hpd)
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{
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return true;
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}
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static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
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enum amdgpu_hpd_id hpd)
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{
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return;
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}
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static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
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{
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return 0;
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}
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/**
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* dce_virtual_bandwidth_update - program display watermarks
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*
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* @adev: amdgpu_device pointer
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*
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* Calculate and program the display watermarks and line
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* buffer allocation (CIK).
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*/
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static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
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{
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return;
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}
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static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
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u16 *green, u16 *blue, uint32_t size,
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struct drm_modeset_acquire_ctx *ctx)
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{
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return 0;
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}
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static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
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{
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struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
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drm_crtc_cleanup(crtc);
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kfree(amdgpu_crtc);
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}
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static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
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.cursor_set2 = NULL,
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.cursor_move = NULL,
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.gamma_set = dce_virtual_crtc_gamma_set,
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.set_config = amdgpu_display_crtc_set_config,
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.destroy = dce_virtual_crtc_destroy,
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.page_flip_target = amdgpu_display_crtc_page_flip_target,
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.get_vblank_counter = amdgpu_get_vblank_counter_kms,
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.enable_vblank = amdgpu_enable_vblank_kms,
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.disable_vblank = amdgpu_disable_vblank_kms,
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.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
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};
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static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct drm_device *dev = crtc->dev;
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struct amdgpu_device *adev = drm_to_adev(dev);
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struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
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unsigned type;
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switch (mode) {
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case DRM_MODE_DPMS_ON:
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amdgpu_crtc->enabled = true;
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/* Make sure VBLANK interrupts are still enabled */
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type = amdgpu_display_crtc_idx_to_irq_type(adev,
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amdgpu_crtc->crtc_id);
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amdgpu_irq_update(adev, &adev->crtc_irq, type);
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drm_crtc_vblank_on(crtc);
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break;
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case DRM_MODE_DPMS_STANDBY:
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case DRM_MODE_DPMS_SUSPEND:
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case DRM_MODE_DPMS_OFF:
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drm_crtc_vblank_off(crtc);
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amdgpu_crtc->enabled = false;
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break;
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}
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}
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static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
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{
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dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
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}
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static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
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{
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dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
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}
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static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
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{
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struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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if (dev->num_crtcs)
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drm_crtc_vblank_off(crtc);
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amdgpu_crtc->enabled = false;
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amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
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amdgpu_crtc->encoder = NULL;
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amdgpu_crtc->connector = NULL;
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}
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static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y, struct drm_framebuffer *old_fb)
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{
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struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
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/* update the hw version fpr dpm */
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amdgpu_crtc->hw_mode = *adjusted_mode;
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return 0;
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}
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static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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return true;
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}
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static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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return 0;
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}
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static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y, enum mode_set_atomic state)
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{
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return 0;
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}
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static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
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.dpms = dce_virtual_crtc_dpms,
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.mode_fixup = dce_virtual_crtc_mode_fixup,
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.mode_set = dce_virtual_crtc_mode_set,
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.mode_set_base = dce_virtual_crtc_set_base,
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.mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
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.prepare = dce_virtual_crtc_prepare,
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.commit = dce_virtual_crtc_commit,
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.disable = dce_virtual_crtc_disable,
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.get_scanout_position = amdgpu_crtc_get_scanout_position,
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};
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static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
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{
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struct amdgpu_crtc *amdgpu_crtc;
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amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
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(AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
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if (amdgpu_crtc == NULL)
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return -ENOMEM;
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drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
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drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
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amdgpu_crtc->crtc_id = index;
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adev->mode_info.crtcs[index] = amdgpu_crtc;
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amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
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amdgpu_crtc->encoder = NULL;
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amdgpu_crtc->connector = NULL;
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amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
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drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
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hrtimer_init(&amdgpu_crtc->vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
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hrtimer_set_expires(&amdgpu_crtc->vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD);
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amdgpu_crtc->vblank_timer.function = dce_virtual_vblank_timer_handle;
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hrtimer_start(&amdgpu_crtc->vblank_timer,
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DCE_VIRTUAL_VBLANK_PERIOD, HRTIMER_MODE_REL);
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return 0;
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}
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static int dce_virtual_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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dce_virtual_set_display_funcs(adev);
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dce_virtual_set_irq_funcs(adev);
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adev->mode_info.num_hpd = 1;
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adev->mode_info.num_dig = 1;
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return 0;
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}
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static struct drm_encoder *
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dce_virtual_encoder(struct drm_connector *connector)
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{
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struct drm_encoder *encoder;
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drm_connector_for_each_possible_encoder(connector, encoder) {
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if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
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return encoder;
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}
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/* pick the first one */
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drm_connector_for_each_possible_encoder(connector, encoder)
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return encoder;
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return NULL;
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}
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static int dce_virtual_get_modes(struct drm_connector *connector)
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{
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struct drm_device *dev = connector->dev;
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struct drm_display_mode *mode = NULL;
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unsigned i;
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static const struct mode_size {
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int w;
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int h;
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} common_modes[] = {
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{ 640, 480},
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{ 720, 480},
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{ 800, 600},
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{ 848, 480},
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{1024, 768},
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{1152, 768},
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{1280, 720},
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{1280, 800},
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{1280, 854},
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{1280, 960},
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{1280, 1024},
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{1440, 900},
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{1400, 1050},
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{1680, 1050},
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{1600, 1200},
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{1920, 1080},
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{1920, 1200},
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{2560, 1440},
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{4096, 3112},
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{3656, 2664},
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{3840, 2160},
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{4096, 2160},
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};
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for (i = 0; i < ARRAY_SIZE(common_modes); i++) {
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mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
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drm_mode_probed_add(connector, mode);
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}
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return 0;
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}
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static enum drm_mode_status dce_virtual_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
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return MODE_OK;
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}
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static int
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dce_virtual_dpms(struct drm_connector *connector, int mode)
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{
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return 0;
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}
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static int
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dce_virtual_set_property(struct drm_connector *connector,
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struct drm_property *property,
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uint64_t val)
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{
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return 0;
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}
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static void dce_virtual_destroy(struct drm_connector *connector)
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{
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drm_connector_unregister(connector);
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drm_connector_cleanup(connector);
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kfree(connector);
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}
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static void dce_virtual_force(struct drm_connector *connector)
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{
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return;
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}
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static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
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.get_modes = dce_virtual_get_modes,
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.mode_valid = dce_virtual_mode_valid,
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.best_encoder = dce_virtual_encoder,
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};
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static const struct drm_connector_funcs dce_virtual_connector_funcs = {
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.dpms = dce_virtual_dpms,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.set_property = dce_virtual_set_property,
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.destroy = dce_virtual_destroy,
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.force = dce_virtual_force,
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};
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const struct drm_mode_config_funcs dce_virtual_mode_funcs = {
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.fb_create = amdgpu_display_user_framebuffer_create,
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.atomic_check = drm_atomic_helper_check,
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@@ -387,10 +48,6 @@ static int dce_virtual_sw_init(void *handle)
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int r, i;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
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if (r)
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return r;
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adev_to_drm(adev)->max_vblank_count = 0;
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adev_to_drm(adev)->mode_config.funcs = &dce_virtual_mode_funcs;
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@@ -436,9 +93,6 @@ static int dce_virtual_sw_fini(void *handle)
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drm_kms_helper_poll_fini(adev_to_drm(adev));
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drm_mode_config_cleanup(adev_to_drm(adev));
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/* clear crtcs pointer to avoid dce irq finish routine access freed data */
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memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS);
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adev->mode_info.mode_config_initialized = false;
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return 0;
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}
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@@ -498,7 +152,7 @@ static int dce_virtual_suspend(void *handle)
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int r;
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r = amdgpu_display_suspend_helper(adev);
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r = drm_mode_config_helper_suspend(adev_to_drm(adev));
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if (r)
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return r;
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return dce_virtual_hw_fini(handle);
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@@ -512,7 +166,7 @@ static int dce_virtual_resume(void *handle)
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r = dce_virtual_hw_init(handle);
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if (r)
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return r;
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return amdgpu_display_resume_helper(adev);
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return drm_mode_config_helper_resume(adev_to_drm(adev));
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}
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static bool dce_virtual_is_idle(void *handle)
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@@ -544,7 +198,7 @@ static int dce_virtual_set_powergating_state(void *handle,
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static const struct amd_ip_funcs dce_virtual_ip_funcs = {
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.name = "dce_virtual",
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.early_init = dce_virtual_early_init,
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.early_init = NULL,
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.late_init = NULL,
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.sw_init = dce_virtual_sw_init,
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.sw_fini = dce_virtual_sw_fini,
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@@ -559,222 +213,6 @@ static const struct amd_ip_funcs dce_virtual_ip_funcs = {
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.set_powergating_state = dce_virtual_set_powergating_state,
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};
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/* these are handled by the primary encoders */
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static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
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{
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return;
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}
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static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
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{
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return;
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}
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static void
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dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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return;
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}
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static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
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{
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return;
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}
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static void
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dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
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{
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return;
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}
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static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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return true;
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}
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static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
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.dpms = dce_virtual_encoder_dpms,
|
||||
.mode_fixup = dce_virtual_encoder_mode_fixup,
|
||||
.prepare = dce_virtual_encoder_prepare,
|
||||
.mode_set = dce_virtual_encoder_mode_set,
|
||||
.commit = dce_virtual_encoder_commit,
|
||||
.disable = dce_virtual_encoder_disable,
|
||||
};
|
||||
|
||||
static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
|
||||
{
|
||||
drm_encoder_cleanup(encoder);
|
||||
kfree(encoder);
|
||||
}
|
||||
|
||||
static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
|
||||
.destroy = dce_virtual_encoder_destroy,
|
||||
};
|
||||
|
||||
static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
|
||||
int index)
|
||||
{
|
||||
struct drm_encoder *encoder;
|
||||
struct drm_connector *connector;
|
||||
|
||||
/* add a new encoder */
|
||||
encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
|
||||
if (!encoder)
|
||||
return -ENOMEM;
|
||||
encoder->possible_crtcs = 1 << index;
|
||||
drm_encoder_init(adev_to_drm(adev), encoder, &dce_virtual_encoder_funcs,
|
||||
DRM_MODE_ENCODER_VIRTUAL, NULL);
|
||||
drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
|
||||
|
||||
connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
|
||||
if (!connector) {
|
||||
kfree(encoder);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* add a new connector */
|
||||
drm_connector_init(adev_to_drm(adev), connector, &dce_virtual_connector_funcs,
|
||||
DRM_MODE_CONNECTOR_VIRTUAL);
|
||||
drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
|
||||
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
|
||||
connector->interlace_allowed = false;
|
||||
connector->doublescan_allowed = false;
|
||||
|
||||
/* link them */
|
||||
drm_connector_attach_encoder(connector, encoder);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
|
||||
.bandwidth_update = &dce_virtual_bandwidth_update,
|
||||
.vblank_get_counter = &dce_virtual_vblank_get_counter,
|
||||
.backlight_set_level = NULL,
|
||||
.backlight_get_level = NULL,
|
||||
.hpd_sense = &dce_virtual_hpd_sense,
|
||||
.hpd_set_polarity = &dce_virtual_hpd_set_polarity,
|
||||
.hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
|
||||
.page_flip = &dce_virtual_page_flip,
|
||||
.page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
|
||||
.add_encoder = NULL,
|
||||
.add_connector = NULL,
|
||||
};
|
||||
|
||||
static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
adev->mode_info.funcs = &dce_virtual_display_funcs;
|
||||
}
|
||||
|
||||
static int dce_virtual_pageflip(struct amdgpu_device *adev,
|
||||
unsigned crtc_id)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct amdgpu_crtc *amdgpu_crtc;
|
||||
struct amdgpu_flip_work *works;
|
||||
|
||||
amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
|
||||
|
||||
if (crtc_id >= adev->mode_info.num_crtc) {
|
||||
DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* IRQ could occur when in initial stage */
|
||||
if (amdgpu_crtc == NULL)
|
||||
return 0;
|
||||
|
||||
spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
|
||||
works = amdgpu_crtc->pflip_works;
|
||||
if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
|
||||
DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
|
||||
"AMDGPU_FLIP_SUBMITTED(%d)\n",
|
||||
amdgpu_crtc->pflip_status,
|
||||
AMDGPU_FLIP_SUBMITTED);
|
||||
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* page flip completed. clean up */
|
||||
amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
|
||||
amdgpu_crtc->pflip_works = NULL;
|
||||
|
||||
/* wakeup usersapce */
|
||||
if (works->event)
|
||||
drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
|
||||
|
||||
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
|
||||
|
||||
drm_crtc_vblank_put(&amdgpu_crtc->base);
|
||||
amdgpu_bo_unref(&works->old_abo);
|
||||
kfree(works->shared);
|
||||
kfree(works);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
|
||||
{
|
||||
struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
|
||||
struct amdgpu_crtc, vblank_timer);
|
||||
struct drm_device *ddev = amdgpu_crtc->base.dev;
|
||||
struct amdgpu_device *adev = drm_to_adev(ddev);
|
||||
struct amdgpu_irq_src *source = adev->irq.client[AMDGPU_IRQ_CLIENTID_LEGACY].sources
|
||||
[VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER];
|
||||
int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
|
||||
amdgpu_crtc->crtc_id);
|
||||
|
||||
if (amdgpu_irq_enabled(adev, source, irq_type)) {
|
||||
drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
|
||||
dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
|
||||
}
|
||||
hrtimer_start(vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD,
|
||||
HRTIMER_MODE_REL);
|
||||
|
||||
return HRTIMER_NORESTART;
|
||||
}
|
||||
|
||||
static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
|
||||
int crtc,
|
||||
enum amdgpu_interrupt_state state)
|
||||
{
|
||||
if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
|
||||
DRM_DEBUG("invalid crtc %d\n", crtc);
|
||||
return;
|
||||
}
|
||||
|
||||
adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
|
||||
DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
|
||||
}
|
||||
|
||||
|
||||
static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
|
||||
struct amdgpu_irq_src *source,
|
||||
unsigned type,
|
||||
enum amdgpu_interrupt_state state)
|
||||
{
|
||||
if (type > AMDGPU_CRTC_IRQ_VBLANK6)
|
||||
return -EINVAL;
|
||||
|
||||
dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
|
||||
.set = dce_virtual_set_crtc_irq_state,
|
||||
.process = NULL,
|
||||
};
|
||||
|
||||
static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
adev->crtc_irq.num_types = adev->mode_info.num_crtc;
|
||||
adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
|
||||
}
|
||||
|
||||
const struct amdgpu_ip_block_version dce_virtual_ip_block =
|
||||
{
|
||||
.type = AMD_IP_BLOCK_TYPE_DCE,
|
||||
|
||||
Reference in New Issue
Block a user