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drm/amdgpu: force complete the KIQ ring fences on reset

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Like the MES scheduler ring, the KIQ ring sets no_scheduler = true and uses a
polling fence, so it is skipped by the force-completion loop in
amdgpu_device_pre_asic_reset(). Its hw fence value lives in wb (GTT) memory and
survives a MODE1 reset while fence_drv.sync_seq keeps advancing, so after a
reset the first KIQ submission can poll forever on a seq that is never written
back.

Force complete the KIQ ring fences too so their hw fence is realigned to
sync_seq.

Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jesse Zhang
2026-08-13 12:28:04 +08:00
committed by Alex Deucher
parent 556488b086
commit fd65d17429
1 changed files with 12 additions and 0 deletions
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12
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
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@@ -5056,6 +5056,18 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
amdgpu_fence_driver_force_completion(mes_ring, fence);
}
/*
* KIQ rings are polling-fence/no_scheduler like MES, so realign their
* fence too (one ring per XCC), otherwise the first post-reset KIQ
* submission polls forever on a stale seq.
*/
for (i = 0; i < AMDGPU_MAX_GC_INSTANCES; i++) {
struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[i].ring;
if (kiq_ring->fence_drv.initialized && kiq_ring->sched.ready)
amdgpu_fence_driver_force_completion(kiq_ring, fence);
}
amdgpu_fence_driver_isr_toggle(adev, false);
r = amdgpu_reset_prepare_hwcontext(adev, reset_context);