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drm/amd/display: Add DCN42B VID_CRC_CONTROL and HBLANK_CONTROL registers

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[why]

These registers are needed by our existing code.

[how]

Add the missing register defines to dcn42b_resource.c.

Remove DCN42B variant of HP_DP_STREAM_ENC_REG_LIST_RI as it is now the
same as the DCN42B one, when these registers are included.

Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Matthew Stewart
2026-06-24 14:59:20 -04:00
committed by Alex Deucher
parent b6f466c509
commit fd651b9a3b
2 changed files with 14 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
View File

@@ -134,6 +134,19 @@
#define regHUBP3_HUBPREQ_DEBUG 0x088d
#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687
#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b
#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f
#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b
#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f
#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2
#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813
#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2
enum dcn401_clk_src_array_id {
DCN401_CLK_SRC_PLL0,
DCN401_CLK_SRC_PLL1,
@@ -351,7 +364,7 @@ static const struct dcn10_link_enc_mask le_mask = {
LINK_ENCODER_MASK_SH_LIST_DCN42B(_MASK)};
#define hpo_dp_stream_encoder_reg_init(id) \
DCN42B_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];

40
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
View File

@@ -254,46 +254,6 @@
SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id),\
SRI_ARR(DIG_FE_AUDIO_CNTL, DIG, id)
/* HPO DP stream encoder */
/* Not in DCN42B:
* SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id),
* SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id),
*/
#define DCN42B_HPO_DP_STREAM_ENC_REG_LIST_RI(id) \
SR_ARR(DP_STREAM_MAPPER_CONTROL0, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL1, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL2, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL3, id), \
SRI_ARR(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id), \
SRI_ARR(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id), \
SRI_ARR(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id), \
SRI_ARR(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id), \
SRI_ARR(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id)
/*HPO DP link encoder regs */
#define DCN42B_HPO_DP_LINK_ENC_REG_LIST_RI(id) \
SRI_ARR(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \