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Merge tag 'thead-dt-for-v6.13' of https://github.com/pdp7/linux into soc/dt

Browse Source 
T-HEAD Devicetrees for v6.13

Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. The
yaml binding and pinctrl-th1520 driver has been merged into next by
Linus W and will be included in the 6.13 pinctrl PR.

The TH1520 GPIO controllers are already supported by the gpio-dwapb
driver. This PR improves GPIO support by adding GPIO ranges and GPIO
line names for the BeagleV Ahead and LicheePi 4A boards. Support is
added for the built-in LEDs on the Ahead board.

Signed-off-by: Drew Fustini <drew@pdp7.com>

* tag 'thead-dt-for-v6.13' of https://github.com/pdp7/linux:
  riscv: dts: thead: remove enabled property for spi0
  riscv: dts: thead: Add missing GPIO clock-names
  riscv: dtb: thead: Add BeagleV Ahead LEDs
  riscv: dts: thead: Add TH1520 pinctrl settings for UART0
  riscv: dts: thead: Add Lichee Pi 4M GPIO line names
  riscv: dts: thead: Adjust TH1520 GPIO labels
  riscv: dts: thead: Add TH1520 GPIO ranges
  riscv: dts: thead: Add TH1520 pin control nodes
This commit is contained in:
Arnd Bergmann
2024-11-12 22:25:27 +01:00
parent 42f7652d3e 2a3bf75a94
commit fce30430a4
4 changed files with 202 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

86
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
View File

@@ -7,6 +7,8 @@
/dts-v1/;
#include "th1520.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
model = "BeagleV Ahead";
@@ -17,6 +19,8 @@ aliases {
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
gpio5 = &aogpio;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -33,7 +37,42 @@ chosen {
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x1 0x00000000>;
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
compatible = "gpio-leds";
led-1 {
gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
label = "led1";
};
led-2 {
gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
label = "led2";
};
led-3 {
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
label = "led3";
};
led-4 {
gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
label = "led4";
};
led-5 {
gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
label = "led5";
};
};
};
@@ -59,6 +98,47 @@ &emmc {
status = "okay";
};
&padctrl_aosys {
led_pins: led-0 {
led-pins {
pins = "AUDIO_PA8", /* GPIO4_8 */
"AUDIO_PA9", /* GPIO4_9 */
"AUDIO_PA10", /* GPIO4_10 */
"AUDIO_PA11", /* GPIO4_11 */
"AUDIO_PA12"; /* GPIO4_12 */
bias-disable;
drive-strength = <3>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&padctrl0_apsys {
uart0_pins: uart0-0 {
tx-pins {
pins = "UART0_TXD";
function = "uart";
bias-disable;
drive-strength = <3>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = "UART0_RXD";
function = "uart";
bias-pull-up;
drive-strength = <1>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
};
&sdio0 {
bus-width = <4>;
max-frequency = <198000000>;
@@ -66,9 +146,7 @@ &sdio0 {
};
&uart0 {
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};

39
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
View File

@@ -25,6 +25,12 @@ &osc_32k {
clock-frequency = <32768>;
};
&aogpio {
gpio-line-names = "", "", "",
"GPIO00",
"GPIO04";
};
&dmac0 {
status = "okay";
};
@@ -39,6 +45,39 @@ &emmc {
status = "okay";
};
&gpio0 {
gpio-line-names = "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "",
"GPIO07",
"GPIO08",
"",
"GPIO01",
"GPIO02";
};
&gpio1 {
gpio-line-names = "", "", "",
"GPIO11",
"GPIO12",
"GPIO13",
"GPIO14",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "",
"GPIO06";
};
&gpio2 {
gpio-line-names = "GPIO03",
"GPIO05";
};
&gpio3 {
gpio-line-names = "", "",
"GPIO09",
"GPIO10";
};
&sdio0 {
bus-width = <4>;
max-frequency = <198000000>;

30
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
View File

@@ -14,6 +14,8 @@ aliases {
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
gpio5 = &aogpio;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -28,10 +30,32 @@ chosen {
};
};
&uart0 {
status = "okay";
&padctrl0_apsys {
uart0_pins: uart0-0 {
tx-pins {
pins = "UART0_TXD";
function = "uart";
bias-disable;
drive-strength = <3>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = "UART0_RXD";
function = "uart";
bias-disable;
drive-strength = <1>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
};
&spi0 {
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};

70
arch/riscv/boot/dts/thead/th1520.dtsi
View File

@@ -216,6 +216,13 @@ osc_32k: 32k-oscillator {
#clock-cells = <0>;
};
aonsys_clk: clock-73728000 {
compatible = "fixed-clock";
clock-frequency = <73728000>;
clock-output-names = "aonsys_clk";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -316,18 +323,20 @@ uart3: serial@ffe7f04000 {
status = "disabled";
};
gpio2: gpio@ffe7f34000 {
gpio@ffe7f34000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f34000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO2>;
clock-names = "bus";
portc: gpio-controller@0 {
gpio2: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
gpio-ranges = <&padctrl0_apsys 0 0 32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -335,18 +344,20 @@ portc: gpio-controller@0 {
};
};
gpio3: gpio@ffe7f38000 {
gpio@ffe7f38000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f38000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO3>;
clock-names = "bus";
portd: gpio-controller@0 {
gpio3: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
ngpios = <23>;
gpio-ranges = <&padctrl0_apsys 0 32 23>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -354,18 +365,27 @@ portd: gpio-controller@0 {
};
};
gpio0: gpio@ffec005000 {
padctrl1_apsys: pinctrl@ffe7f3c000 {
compatible = "thead,th1520-pinctrl";
reg = <0xff 0xe7f3c000 0x0 0x1000>;
clocks = <&clk CLK_PADCTRL1>;
thead,pad-group = <2>;
};
gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO0>;
clock-names = "bus";
porta: gpio-controller@0 {
gpio0: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
gpio-ranges = <&padctrl1_apsys 0 0 32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -373,18 +393,20 @@ porta: gpio-controller@0 {
};
};
gpio1: gpio@ffec006000 {
gpio@ffec006000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec006000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO1>;
clock-names = "bus";
portb: gpio-controller@0 {
gpio1: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
ngpios = <31>;
gpio-ranges = <&padctrl1_apsys 0 32 31>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -392,6 +414,13 @@ portb: gpio-controller@0 {
};
};
padctrl0_apsys: pinctrl@ffec007000 {
compatible = "thead,th1520-pinctrl";
reg = <0xff 0xec007000 0x0 0x1000>;
clocks = <&clk CLK_PADCTRL0>;
thead,pad-group = <3>;
};
uart2: serial@ffec010000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xec010000 0x0 0x4000>;
@@ -520,17 +549,18 @@ timer7: timer@ffffc3303c {
status = "disabled";
};
ao_gpio0: gpio@fffff41000 {
gpio@fffff41000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff41000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
porte: gpio-controller@0 {
aogpio: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
ngpios = <16>;
gpio-ranges = <&padctrl_aosys 0 9 16>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -538,17 +568,25 @@ porte: gpio-controller@0 {
};
};
ao_gpio1: gpio@fffff52000 {
padctrl_aosys: pinctrl@fffff4a000 {
compatible = "thead,th1520-pinctrl";
reg = <0xff 0xfff4a000 0x0 0x2000>;
clocks = <&aonsys_clk>;
thead,pad-group = <1>;
};
gpio@fffff52000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff52000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
portf: gpio-controller@0 {
gpio4: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
ngpios = <23>;
gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;