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drm/msm/a6xx: Fix A663 GPUCC register list for state capture

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The GPUCC register list for A663 is incorrect, which can cause
out-of-bounds register access during GPU state capture.

Update it to use the correct register ranges.

Fixes: 5773cce861 ("drm/msm/a6xx: Add support for A663")
Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/730656/
Message-ID: <20260605-assorted-fixes-june-v1-3-2caa04f7287c@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Jie Zhang
2026-06-05 01:38:19 +05:30
committed by Rob Clark
parent b303e1d528
commit fc7ccbc617
1 changed files with 3 additions and 1 deletions
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4
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
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@@ -1244,7 +1244,9 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1],
&a6xx_state->gmu_registers[1], true);
if (adreno_is_a621(adreno_gpu) || adreno_is_a623(adreno_gpu))
if (adreno_is_a621(adreno_gpu) ||
adreno_is_a623(adreno_gpu) ||
adreno_is_a663(adreno_gpu))
_a6xx_get_gmu_registers(gpu, a6xx_state, &a621_gpucc_reg,
&a6xx_state->gmu_registers[2], false);
else