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Merge tag 'v5.18-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

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Some corrections for the rk80x pmic nodes, a supply fix for rk3399-firefly
and addition of the usb/sata combophys for rk3568.

* tag 'v5.18-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: Add #clock-cells value for rk805
  arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808
  arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly
  arm64: dts: rockchip: add naneng combo phy nodes for rk3568

Link: https://lore.kernel.org/r/13959624.7hp8jFWaoN@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-03-10 09:32:23 +01:00
parent 7b4fc7c6f9 9d25aadd55
commit fc30ed4edd
6 changed files with 71 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm64/boot/dts/rockchip/rk3328-a1.dts
View File

@@ -160,6 +160,7 @@ pmic@18 {
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <0>;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;

4
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
View File

@@ -775,8 +775,8 @@ &sdio0 {
sd-uhs-sdr104;
/* Power supply */
vqmmc-supply = &vcc1v8_s3; /* IO line */
vmmc-supply = &vcc_sdio; /* card's power */
vqmmc-supply = <&vcc1v8_s3>; /* IO line */
vmmc-supply = <&vcc_sdio>; /* card's power */
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
View File

@@ -472,8 +472,6 @@ rk808: pmic@1b {
vcc10-supply = <&vcc_sysin>;
vcc11-supply = <&vcc_sysin>;
vcc12-supply = <&vcc3v3_sys>;
vcc13-supply = <&vcc_sysin>;
vcc14-supply = <&vcc_sysin>;
regulators {
/* rk3399 center logic supply */

2
arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
View File

@@ -310,8 +310,6 @@ rk808: pmic@1b {
vcc10-supply = <&vcc3v3_sys>;
vcc11-supply = <&vcc3v3_sys>;
vcc12-supply = <&vcc3v3_sys>;
vcc13-supply = <&vcc3v3_sys>;
vcc14-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_3v0>;
regulators {

21
arch/arm64/boot/dts/rockchip/rk3568.dtsi
View File

@@ -8,6 +8,11 @@
/ {
compatible = "rockchip,rk3568";
pipe_phy_grf0: syscon@fdc70000 {
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
reg = <0x0 0xfdc70000 0x0 0x1000>;
};
qos_pcie3x1: qos@fe190080 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190080 0x0 0x20>;
@@ -71,6 +76,22 @@ gmac0_mtl_tx_setup: tx-queues-config {
queue0 {};
};
};
combphy0: phy@fe820000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe820000 0x0 0x100>;
clocks = <&pmucru CLK_PCIEPHY0_REF>,
<&cru PCLK_PIPEPHY0>,
<&cru PCLK_PIPE>;
clock-names = "ref", "apb", "pipe";
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_PIPEPHY0>;
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
#phy-cells = <1>;
status = "disabled";
};
};
&cpu0_opp_table {

47
arch/arm64/boot/dts/rockchip/rk356x.dtsi
View File

@@ -296,11 +296,26 @@ pmu_io_domains: io-domains {
};
};
pipegrf: syscon@fdc50000 {
compatible = "rockchip,rk3568-pipe-grf", "syscon";
reg = <0x0 0xfdc50000 0x0 0x1000>;
};
grf: syscon@fdc60000 {
compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
reg = <0x0 0xfdc60000 0x0 0x10000>;
};
pipe_phy_grf1: syscon@fdc80000 {
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
reg = <0x0 0xfdc80000 0x0 0x1000>;
};
pipe_phy_grf2: syscon@fdc90000 {
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
reg = <0x0 0xfdc90000 0x0 0x1000>;
};
usb2phy0_grf: syscon@fdca0000 {
compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
reg = <0x0 0xfdca0000 0x0 0x8000>;
@@ -1307,6 +1322,38 @@ pwm15: pwm@fe700030 {
status = "disabled";
};
combphy1: phy@fe830000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe830000 0x0 0x100>;
clocks = <&pmucru CLK_PCIEPHY1_REF>,
<&cru PCLK_PIPEPHY1>,
<&cru PCLK_PIPE>;
clock-names = "ref", "apb", "pipe";
assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_PIPEPHY1>;
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
#phy-cells = <1>;
status = "disabled";
};
combphy2: phy@fe840000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe840000 0x0 0x100>;
clocks = <&pmucru CLK_PCIEPHY2_REF>,
<&cru PCLK_PIPEPHY2>,
<&cru PCLK_PIPE>;
clock-names = "ref", "apb", "pipe";
assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_PIPEPHY2>;
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
#phy-cells = <1>;
status = "disabled";
};
usb2phy0: usb2phy@fe8a0000 {
compatible = "rockchip,rk3568-usb2phy";
reg = <0x0 0xfe8a0000 0x0 0x10000>;