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arm64: dts: rockchip: Move rk3568 PCIe3 MSI to use GIC ITS
Following commit b956c9de91 ("arm64: dts: rockchip: rk356x: Move
PCIe MSI to use GIC ITS instead of MBI"), change the PCIe3 controller's
MSI on rk3568 to use ITS, so that all MSI-X can work properly.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250308093008.568437-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
committed by
Heiko Stuebner
parent
8eca9e979a
commit
fbea35a661
@@ -152,7 +152,7 @@ pcie3x1: pcie@fe270000 {
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compatible = "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xf>;
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bus-range = <0x10 0x1f>;
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clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
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<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
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<&cru CLK_PCIE30X1_AUX_NDFT>;
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@@ -175,7 +175,7 @@ pcie3x1: pcie@fe270000 {
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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max-link-speed = <3>;
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msi-map = <0x0 &gic 0x1000 0x1000>;
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msi-map = <0x1000 &its 0x1000 0x1000>;
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num-lanes = <1>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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@@ -205,7 +205,7 @@ pcie3x2: pcie@fe280000 {
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compatible = "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xf>;
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bus-range = <0x20 0x2f>;
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clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
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<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
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<&cru CLK_PCIE30X2_AUX_NDFT>;
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@@ -228,7 +228,7 @@ pcie3x2: pcie@fe280000 {
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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max-link-speed = <3>;
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msi-map = <0x0 &gic 0x2000 0x1000>;
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msi-map = <0x2000 &its 0x2000 0x1000>;
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num-lanes = <2>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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