mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-07-22 04:37:32 -04:00
drm/amd/display: Fix DCN42B null registers & register masks
[why]
DCN42B is missing some register masks, which are causing errors in dmesg.
[how]
Make DCN42B reuse the DCN42 register lists, and add the missing defines manually.
Fixes: 64142f9d51af ("drm/amd/display: Fix DCN42 null registers & register masks")
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit b7d69145907cdefcbd39a70a31eefd30919af9f1)
This commit is contained in:
Matthew Stewart
committed by
Alex Deucher
Alex Deucher
parent
29c57db162
commit
fbbbd98f20
@@ -22,6 +22,7 @@
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#include "dcn35/dcn35_resource.h"
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#include "dcn321/dcn321_resource.h"
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#include "dcn401/dcn401_resource.h"
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#include "dcn42/dcn42_resource.h"
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#include "dcn42/dcn42_resource_fpu.h"
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#include "dcn10/dcn10_ipp.h"
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@@ -116,6 +117,23 @@
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#define regAPG9_APG_DBG_GEN_CONTROL 0x38ae
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#define regAPG9_APG_DBG_GEN_CONTROL_BASE_IDX 2
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#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f8
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#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define regHUBP0_HUBPREQ_DEBUG 0x05f9
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#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
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#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d4
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#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define regHUBP1_HUBPREQ_DEBUG 0x06d5
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#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
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#define regHUBP2_HUBPREQ_DEBUG_DB 0x07b0
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#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define regHUBP2_HUBPREQ_DEBUG 0x07b1
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#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2
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#define regHUBP3_HUBPREQ_DEBUG_DB 0x088c
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#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define regHUBP3_HUBPREQ_DEBUG 0x088d
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#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
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enum dcn401_clk_src_array_id {
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DCN401_CLK_SRC_PLL0,
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DCN401_CLK_SRC_PLL1,
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@@ -461,7 +479,7 @@ static const struct dcn_optc_mask optc_mask = {
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OPTC_COMMON_MASK_SH_LIST_DCN42B(_MASK)};
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#define hubp_regs_init(id) \
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HUBP_REG_LIST_DCN42B_RI(id)
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HUBP_REG_LIST_DCN42_RI(id)
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static struct dcn_hubp2_registers hubp_regs[4];
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@@ -344,7 +344,6 @@
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* DCCG_SRII(PHASE, DP_DTO, 3),
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* DCCG_SRII(MODULO, DP_DTO, 3),
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* SR(DSCCLK3_DTO_PARAM),
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* SR(HDMISTREAMCLK_CNTL),
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* SR(SYMCLKD_CLOCK_ENABLE),
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* SR(SYMCLKE_CLOCK_ENABLE)
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*/
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@@ -360,6 +359,7 @@
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SR(PHYBSYMCLK_CLOCK_CNTL), \
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SR(PHYCSYMCLK_CLOCK_CNTL), \
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SR(DPSTREAMCLK_CNTL), \
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SR(HDMISTREAMCLK_CNTL), \
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SR(SYMCLK32_SE_CNTL), \
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SR(SYMCLK32_LE_CNTL), \
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DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), \
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@@ -542,120 +542,6 @@
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SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_DATA, ABM, id), \
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SRI_ARR(DC_ABM1_ACE_PWL_CNTL, ABM, id)
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/* HUBP */
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/* Not in DCN42B: HUBPREQ_DEBUG_DB and HUBPREQ_DEBUG */
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#define HUBP_REG_LIST_DCN42B_RI(id) \
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SRI_ARR(DCN_DMDATA_VM_CNTL, HUBPREQ, id), \
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SRI_ARR(FLIP_PARAMETERS_3, HUBPREQ, id), \
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SRI_ARR(FLIP_PARAMETERS_4, HUBPREQ, id), \
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SRI_ARR(FLIP_PARAMETERS_5, HUBPREQ, id), \
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SRI_ARR(FLIP_PARAMETERS_6, HUBPREQ, id), \
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SRI_ARR(VBLANK_PARAMETERS_5, HUBPREQ, id), \
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SRI_ARR(VBLANK_PARAMETERS_6, HUBPREQ, id), \
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HUBP_REG_LIST_DCN_VM_RI(id), \
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SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id), \
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SRI_ARR(PREFETCH_SETTINGS_C, HUBPREQ, id), \
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SRI_ARR(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id), \
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SRI_ARR(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id), \
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SRI_ARR(CURSOR_SETTINGS, HUBPREQ, id), \
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SRI_ARR(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
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SRI_ARR(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
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SRI_ARR(CURSOR_SIZE, CURSOR0_, id), \
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SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \
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SRI_ARR(CURSOR_POSITION, CURSOR0_, id), \
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SRI_ARR(CURSOR_HOT_SPOT, CURSOR0_, id), \
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SRI_ARR(CURSOR_DST_OFFSET, CURSOR0_, id), \
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SRI_ARR(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \
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SRI_ARR(DMDATA_ADDRESS_LOW, CURSOR0_, id), \
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SRI_ARR(DMDATA_CNTL, CURSOR0_, id), \
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SRI_ARR(DMDATA_SW_CNTL, CURSOR0_, id), \
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SRI_ARR(DMDATA_QOS_CNTL, CURSOR0_, id), \
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SRI_ARR(DMDATA_SW_DATA, CURSOR0_, id), \
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SRI_ARR(DMDATA_STATUS, CURSOR0_, id), \
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SRI_ARR(FLIP_PARAMETERS_0, HUBPREQ, id), \
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SRI_ARR(FLIP_PARAMETERS_1, HUBPREQ, id), \
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SRI_ARR(FLIP_PARAMETERS_2, HUBPREQ, id), \
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SRI_ARR(DCN_CUR1_TTU_CNTL0, HUBPREQ, id), \
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SRI_ARR(DCN_CUR1_TTU_CNTL1, HUBPREQ, id), \
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SRI_ARR(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
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SRI_ARR(VMID_SETTINGS_0, HUBPREQ, id), \
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SRI_ARR(DCHUBP_CNTL, HUBP, id), \
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SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id), \
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SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id), \
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SRI_ARR(DCSURF_SURFACE_PITCH, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_PITCH_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_CONFIG, HUBP, id), \
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SRI_ARR(DCSURF_FLIP_CONTROL, HUBPREQ, id), \
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SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
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SRI_ARR(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
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SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
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SRI_ARR(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
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SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
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SRI_ARR(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
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SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \
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SRI_ARR(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \
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SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
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SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id), \
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SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
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SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id), \
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SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
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SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id), \
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SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
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SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id), \
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SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_INUSE, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_INUSE_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_CONTROL, HUBPREQ, id), \
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SRI_ARR(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id), \
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SRI_ARR(HUBPRET_CONTROL, HUBPRET, id), \
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SRI_ARR(HUBPRET_READ_LINE_STATUS, HUBPRET, id), \
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SRI_ARR(DCN_EXPANSION_MODE, HUBPREQ, id), \
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SRI_ARR(DCHUBP_REQ_SIZE_CONFIG, HUBP, id), \
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SRI_ARR(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id), \
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SRI_ARR(BLANK_OFFSET_0, HUBPREQ, id), \
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SRI_ARR(BLANK_OFFSET_1, HUBPREQ, id), \
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SRI_ARR(DST_DIMENSIONS, HUBPREQ, id), \
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SRI_ARR(DST_AFTER_SCALER, HUBPREQ, id), \
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SRI_ARR(VBLANK_PARAMETERS_0, HUBPREQ, id), \
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SRI_ARR(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id), \
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SRI_ARR(VBLANK_PARAMETERS_1, HUBPREQ, id), \
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SRI_ARR(VBLANK_PARAMETERS_3, HUBPREQ, id), \
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SRI_ARR(NOM_PARAMETERS_4, HUBPREQ, id), \
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SRI_ARR(NOM_PARAMETERS_5, HUBPREQ, id), \
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SRI_ARR(PER_LINE_DELIVERY_PRE, HUBPREQ, id), \
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SRI_ARR(PER_LINE_DELIVERY, HUBPREQ, id), \
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SRI_ARR(VBLANK_PARAMETERS_2, HUBPREQ, id), \
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SRI_ARR(VBLANK_PARAMETERS_4, HUBPREQ, id), \
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SRI_ARR(NOM_PARAMETERS_6, HUBPREQ, id), \
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SRI_ARR(NOM_PARAMETERS_7, HUBPREQ, id), \
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SRI_ARR(DCN_TTU_QOS_WM, HUBPREQ, id), \
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SRI_ARR(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id), \
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SRI_ARR(DCN_SURF0_TTU_CNTL0, HUBPREQ, id), \
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SRI_ARR(DCN_SURF0_TTU_CNTL1, HUBPREQ, id), \
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SRI_ARR(DCN_SURF1_TTU_CNTL0, HUBPREQ, id), \
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SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id), \
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SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id), \
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SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id), \
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SRI_ARR(HUBP_CLK_CNTL, HUBP, id), \
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SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id), \
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SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \
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SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \
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SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \
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SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, id), \
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HUBP_3DLUT_FL_REG_LIST_DCN401(id)
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struct dcn42b_resource_pool {
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struct resource_pool base;
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};
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