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arm64: dts: rockchip: add px30 otp controller

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The px30 soc contains a controller for one-time-programmable memory,
so add the necessary node for it and the fields defined in it by default.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20191023224113.3268-1-heiko@sntech.de
This commit is contained in:
Heiko Stuebner
2019-10-24 00:41:13 +02:00
committed by Heiko Stuebner
parent cec0e350ca
commit fbb78418c8
1 changed files with 24 additions and 0 deletions
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24
arch/arm64/boot/dts/rockchip/px30.dtsi
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@@ -664,6 +664,30 @@ saradc: saradc@ff288000 {
status = "disabled";
};
otp: nvmem@ff290000 {
compatible = "rockchip,px30-otp";
reg = <0x0 0xff290000 0x0 0x4000>;
clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
<&cru PCLK_OTP_PHY>;
clock-names = "otp", "apb_pclk", "phy";
resets = <&cru SRST_OTP_PHY>;
reset-names = "phy";
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
cpu_id: id@7 {
reg = <0x07 0x10>;
};
cpu_leakage: cpu-leakage@17 {
reg = <0x17 0x1>;
};
performance: performance@1e {
reg = <0x1e 0x1>;
bits = <4 3>;
};
};
cru: clock-controller@ff2b0000 {
compatible = "rockchip,px30-cru";
reg = <0x0 0xff2b0000 0x0 0x1000>;