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drm/i915/perf: Save/restore EU flex counters across reset

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If a drm client is killed, then hw contexts used by the client are reset
immediately. This reset clears the EU flex counter configuration. If an
OA use case is running in parallel, it would start seeing zeroed eu
counter values following the reset even if the drm client is restarted.
Save/restore the EU flex counter config so that the EU counters can be
monitored continuously across resets.

v2:
- Save/restore eu flex config only for gen12, as for pre-gen12, these
  are saved and restored in the context image.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-14-umesh.nerlige.ramappa@intel.com
This commit is contained in:
Umesh Nerlige Ramappa
2022-10-26 22:20:59 +00:00
committed by John Harrison
parent bc7ed4d308
commit fa56980434
1 changed files with 10 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
View File

@@ -392,6 +392,16 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
else
ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
if (GRAPHICS_VER(engine->i915) >= 12) {
ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL0, false);
ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL1, false);
ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL2, false);
ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL3, false);
ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL4, false);
ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL5, false);
ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL6, false);
}
return ret ? -1 : 0;
}