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ARM: dts: qcom: stop using snps,dw-pcie falback

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Qualcomm PCIe devices are not really compatible with the snps,dw-pcie.
Unlike the generic IP core, they have special requirements regarding
enabling clocks, toggling resets, using the PHY, etc.

This is not to mention that platform snps-dw-pcie driver expects to find
two IRQs declared, while Qualcomm platforms use just one.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220506152107.1527552-7-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov
2022-05-06 18:21:05 +03:00
committed by Bjorn Andersson
parent 47931796aa
commit f9aad4f098
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/qcom-apq8064.dtsi
View File

@@ -1384,7 +1384,7 @@ gfx3d1: iommu@7d00000 {
};
pcie: pci@1b500000 {
compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
compatible = "qcom,pcie-apq8064";
reg = <0x1b500000 0x1000>,
<0x1b502000 0x80>,
<0x1b600000 0x100>,

2
arch/arm/boot/dts/qcom-ipq4019.dtsi
View File

@@ -412,7 +412,7 @@ restart@4ab000 {
};
pcie0: pci@40000000 {
compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
compatible = "qcom,pcie-ipq4019";
reg = <0x40000000 0xf1d
0x40000f20 0xa8
0x80000 0x2000