mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-04-13 06:10:18 -04:00
Merge tag 'v6.16-rockchip-dts64-3' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
Power-domains needed for stability, dropping of unnecessary assigned-clocks (handled by cpufreq) and fixes for dtc W=1 warnings. * tag 'v6.16-rockchip-dts64-3' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3562 pcie unit addresses arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3576 pcie unit addresses arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588 arm64: dts: rockchip: Add missing SFC power-domains to rk3576 Link: https://lore.kernel.org/r/4798229.ejJDZkT8p0@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -95,6 +95,74 @@ scmi_clk: protocol@14 {
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};
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3528-pinctrl";
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rockchip,grf = <&ioc_grf>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio0: gpio@ff610000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff610000 0x0 0x200>;
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clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@ffaf0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xffaf0000 0x0 0x200>;
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clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 32 32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@ffb00000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xffb00000 0x0 0x200>;
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clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 64 32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@ffb10000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xffb10000 0x0 0x200>;
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clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 96 32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@ffb20000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xffb20000 0x0 0x200>;
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clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 128 32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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@@ -866,74 +934,6 @@ dmac: dma-controller@ffd60000 {
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#dma-cells = <1>;
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arm,pl330-periph-burst;
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3528-pinctrl";
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rockchip,grf = <&ioc_grf>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio0: gpio@ff610000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff610000 0x0 0x200>;
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clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@ffaf0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xffaf0000 0x0 0x200>;
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clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 32 32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@ffb00000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xffb00000 0x0 0x200>;
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clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 64 32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@ffb10000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xffb10000 0x0 0x200>;
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clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 96 32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@ffb20000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xffb20000 0x0 0x200>;
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clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 128 32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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};
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};
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@@ -218,6 +218,74 @@ scmi_clk: protocol@14 {
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};
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3562-pinctrl";
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rockchip,grf = <&ioc_grf>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio0: gpio@ff260000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff260000 0x0 0x100>;
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clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 32>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@ff620000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff620000 0x0 0x100>;
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clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 32 32>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@ff630000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff630000 0x0 0x100>;
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clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 64 32>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@ffac0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xffac0000 0x0 0x100>;
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clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 96 32>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@ffad0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xffad0000 0x0 0x100>;
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clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 128 32>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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@@ -249,6 +317,59 @@ soc {
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#size-cells = <2>;
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ranges;
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pcie2x1: pcie@fe000000 {
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compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie";
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reg = <0x0 0xfe000000 0x0 0x400000>,
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<0x0 0xff500000 0x0 0x10000>,
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<0x0 0xfc000000 0x0 0x100000>;
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reg-names = "dbi", "apb", "config";
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bus-range = <0x0 0xff>;
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clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
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<&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
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<&cru CLK_PCIE20_AUX>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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device_type = "pci";
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
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<0 0 0 2 &pcie2x1_intc 1>,
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<0 0 0 3 &pcie2x1_intc 2>,
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<0 0 0 4 &pcie2x1_intc 3>;
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linux,pci-domain = <0>;
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max-link-speed = <2>;
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num-ib-windows = <8>;
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num-viewport = <8>;
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num-ob-windows = <2>;
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num-lanes = <1>;
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phys = <&combphy PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power 15>;
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ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
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0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
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0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
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resets = <&cru SRST_PCIE20_POWERUP>;
|
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reset-names = "pipe";
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
|
||||
|
||||
pcie2x1_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@fe901000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
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||||
@@ -621,59 +742,6 @@ gpu: gpu@ff320000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie2x1: pcie@ff500000 {
|
||||
compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie";
|
||||
bus-range = <0x0 0xff>;
|
||||
clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
|
||||
<&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
|
||||
<&cru CLK_PCIE20_AUX>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk", "aux";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
|
||||
<0 0 0 2 &pcie2x1_intc 1>,
|
||||
<0 0 0 3 &pcie2x1_intc 2>,
|
||||
<0 0 0 4 &pcie2x1_intc 3>;
|
||||
linux,pci-domain = <0>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-viewport = <8>;
|
||||
num-ob-windows = <2>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power 15>;
|
||||
ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
|
||||
0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
|
||||
0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
|
||||
reg = <0x0 0xfe000000 0x0 0x400000>,
|
||||
<0x0 0xff500000 0x0 0x10000>,
|
||||
<0x0 0xfc000000 0x0 0x100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE20_POWERUP>;
|
||||
reset-names = "pipe";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
pcie2x1_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
spi1: spi@ff640000 {
|
||||
compatible = "rockchip,rk3066-spi";
|
||||
reg = <0x0 0xff640000 0x0 0x1000>;
|
||||
@@ -1111,74 +1179,6 @@ saradc1: adc@ffaa0000 {
|
||||
#io-channel-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3562-pinctrl";
|
||||
rockchip,grf = <&ioc_grf>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio@ff260000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xff260000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@ff620000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xff620000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 32 32>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@ff630000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xff630000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 64 32>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@ffac0000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xffac0000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 96 32>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@ffad0000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xffad0000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 128 32>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -429,6 +429,74 @@ simple-audio-card,cpu {
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3576-pinctrl";
|
||||
rockchip,grf = <&ioc_grf>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio@27320000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0x27320000 0x0 0x200>;
|
||||
clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2ae10000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0x2ae10000 0x0 0x200>;
|
||||
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 32 32>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2ae20000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0x2ae20000 0x0 0x200>;
|
||||
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 64 32>;
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@2ae30000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0x2ae30000 0x0 0x200>;
|
||||
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 96 32>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@2ae40000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0x2ae40000 0x0 0x200>;
|
||||
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 128 32>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu_a53: pmu-a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@@ -466,6 +534,114 @@ soc {
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
pcie0: pcie@22000000 {
|
||||
compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
|
||||
reg = <0x0 0x22000000 0x0 0x00400000>,
|
||||
<0x0 0x2a200000 0x0 0x00010000>,
|
||||
<0x0 0x20000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
bus-range = <0x0 0xf>;
|
||||
clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
|
||||
<&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
|
||||
<&cru CLK_PCIE0_AUX>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
|
||||
<0 0 0 2 &pcie0_intc 1>,
|
||||
<0 0 0 3 &pcie0_intc 2>,
|
||||
<0 0 0 4 &pcie0_intc 3>;
|
||||
linux,pci-domain = <0>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-viewport = <8>;
|
||||
num-ob-windows = <2>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy0_ps PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3576_PD_PHP>;
|
||||
ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
|
||||
0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
|
||||
0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
|
||||
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
||||
reset-names = "pwr", "pipe";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
pcie0_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@22400000 {
|
||||
compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
|
||||
reg = <0x0 0x22400000 0x0 0x00400000>,
|
||||
<0x0 0x2a210000 0x0 0x00010000>,
|
||||
<0x0 0x21000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
bus-range = <0x20 0x2f>;
|
||||
clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
|
||||
<&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
|
||||
<&cru CLK_PCIE1_AUX>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
|
||||
<0 0 0 2 &pcie1_intc 1>,
|
||||
<0 0 0 3 &pcie1_intc 2>,
|
||||
<0 0 0 4 &pcie1_intc 3>;
|
||||
linux,pci-domain = <0>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-viewport = <8>;
|
||||
num-ob-windows = <2>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy1_psu PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3576_PD_SUBPHP>;
|
||||
ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
|
||||
0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
|
||||
0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
|
||||
resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
||||
reset-names = "pwr", "pipe";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
pcie1_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_drd0_dwc3: usb@23000000 {
|
||||
compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0x23000000 0x0 0x400000>;
|
||||
@@ -1343,114 +1519,6 @@ qos_npu_m1ro: qos@27f22100 {
|
||||
reg = <0x0 0x27f22100 0x0 0x20>;
|
||||
};
|
||||
|
||||
pcie0: pcie@2a200000 {
|
||||
compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
|
||||
reg = <0x0 0x22000000 0x0 0x00400000>,
|
||||
<0x0 0x2a200000 0x0 0x00010000>,
|
||||
<0x0 0x20000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
bus-range = <0x0 0xf>;
|
||||
clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
|
||||
<&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
|
||||
<&cru CLK_PCIE0_AUX>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
|
||||
<0 0 0 2 &pcie0_intc 1>,
|
||||
<0 0 0 3 &pcie0_intc 2>,
|
||||
<0 0 0 4 &pcie0_intc 3>;
|
||||
linux,pci-domain = <0>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-viewport = <8>;
|
||||
num-ob-windows = <2>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy0_ps PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3576_PD_PHP>;
|
||||
ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
|
||||
0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
|
||||
0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
|
||||
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
||||
reset-names = "pwr", "pipe";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
pcie0_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@2a210000 {
|
||||
compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
|
||||
reg = <0x0 0x22400000 0x0 0x00400000>,
|
||||
<0x0 0x2a210000 0x0 0x00010000>,
|
||||
<0x0 0x21000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
bus-range = <0x20 0x2f>;
|
||||
clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
|
||||
<&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
|
||||
<&cru CLK_PCIE1_AUX>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
|
||||
<0 0 0 2 &pcie1_intc 1>,
|
||||
<0 0 0 3 &pcie1_intc 2>,
|
||||
<0 0 0 4 &pcie1_intc 3>;
|
||||
linux,pci-domain = <0>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-viewport = <8>;
|
||||
num-ob-windows = <2>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy1_psu PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3576_PD_SUBPHP>;
|
||||
ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
|
||||
0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
|
||||
0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
|
||||
resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
||||
reset-names = "pwr", "pipe";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
pcie1_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac0: ethernet@2a220000 {
|
||||
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0x2a220000 0x0 0x10000>;
|
||||
@@ -1605,6 +1673,7 @@ sfc1: spi@2a300000 {
|
||||
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>;
|
||||
clock-names = "clk_sfc", "hclk_sfc";
|
||||
power-domains = <&power RK3576_PD_SDGMAC>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@@ -1655,6 +1724,7 @@ sfc0: spi@2a340000 {
|
||||
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>;
|
||||
clock-names = "clk_sfc", "hclk_sfc";
|
||||
power-domains = <&power RK3576_PD_NVM>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@@ -1932,7 +2002,6 @@ i2c5: i2c@2ac80000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
i2c6: i2c@2ac90000 {
|
||||
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0x2ac90000 0x0 0x1000>;
|
||||
@@ -2347,74 +2416,6 @@ scmi_shmem: scmi-shmem@4010f000 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x0 0x4010f000 0x0 0x100>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3576-pinctrl";
|
||||
rockchip,grf = <&ioc_grf>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio@27320000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0x27320000 0x0 0x200>;
|
||||
clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2ae10000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0x2ae10000 0x0 0x200>;
|
||||
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 32 32>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2ae20000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0x2ae20000 0x0 0x200>;
|
||||
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 64 32>;
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@2ae30000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0x2ae30000 0x0 0x200>;
|
||||
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 96 32>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@2ae40000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0x2ae40000 0x0 0x200>;
|
||||
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 128 32>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -96,8 +96,6 @@ cpu_l0: cpu@0 {
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <530>;
|
||||
clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
||||
assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
||||
assigned-clock-rates = <816000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-line-size = <64>;
|
||||
@@ -174,8 +172,6 @@ cpu_b0: cpu@400 {
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
|
||||
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
|
||||
assigned-clock-rates = <816000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-line-size = <64>;
|
||||
@@ -214,8 +210,6 @@ cpu_b2: cpu@600 {
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
|
||||
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
|
||||
assigned-clock-rates = <816000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-line-size = <64>;
|
||||
|
||||
Reference in New Issue
Block a user