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drm/xe/migrate: Revamp PAT index selection for migrate PTEs

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Improve PAT index selection logic in xe_migrate.c to avoid unnecessary
coherency overhead when host-side memory is uncached. Previously,
we defaulted to XE_CACHE_WB, which enforces 2-way coherency and may
trigger cacheline pulls from CPU even when host-side memory is never
dirty.

This change introduces xe_migrate_pat_index() to choose the appropriate
PAT index based on the actual TTM caching mode of the buffer object
being mapped. For iGPUs with WC host mappings, we now prefer
XE_CACHE_NONE to skip coherency snoops. For compressed PTEs on newer
platforms, we select XE_CACHE_NONE_COMPRESSION.

This avoids unnecessary cache traffic for uncached host mappings.

v6: (sashiko)
- Only apply the BO's host-side caching for system-memory PTEs.

v5: (Matt A)
- Simplify emit_pte() to derive caching from res->bo directly, removing
  the separate bo parameter
- Leave changes in __xe_migrate_update_pgtables() and
  build_pt_update_batch_sram()
- Fix comment about page-walker coherency in xe_migrate_pat_index()

v4:
- Keep xe_migrate_prepare_vm() on XE_CACHE_WB since page tables require
  page-walker coherency.
- Pass BO into emit_pte() and select PAT attributes from the BO's TTM
  caching mode.

Assisted-by: Github-Copilot:claude-opus-4.8
Signed-off-by: Sanjay Yadav <sanjay.kumar.yadav@intel.com>
Suggested-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20260710083004.1546599-2-sanjay.kumar.yadav@intel.com
This commit is contained in:
Sanjay Yadav
2026-07-10 14:00:05 +05:30
committed by Matthew Auld
parent 942cbdcc8c
commit f922412260
1 changed files with 27 additions and 6 deletions
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33
drivers/gpu/drm/xe/xe_migrate.c
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@@ -117,6 +117,27 @@ static void xe_migrate_fini(void *arg)
xe_exec_queue_put(m->q);
}
static inline u16 xe_migrate_pat_index(struct xe_device *xe,
enum ttm_caching caching,
bool is_comp_pte)
{
enum xe_cache_level cache_level;
/*
* Select the appropriate PAT index for buffer object PTEs programmed
* by emit_pte(). We choose not to mess with xe_migrate_prepare_vm()
* yet, for simplicity.
*/
if (is_comp_pte && GRAPHICS_VERx100(xe) >= 2000)
cache_level = XE_CACHE_NONE_COMPRESSION;
else if (caching == ttm_cached)
cache_level = XE_CACHE_WB;
else
cache_level = XE_CACHE_NONE;
return xe_cache_pat_idx(xe, cache_level);
}
static u64 xe_migrate_vm_addr(u64 slot, u32 level)
{
XE_WARN_ON(slot >= NUM_PT_SLOTS);
@@ -607,17 +628,17 @@ static void emit_pte(struct xe_migrate *m,
{
struct xe_device *xe = tile_to_xe(m->tile);
struct xe_vm *vm = m->q->vm;
struct xe_bo *bo = ttm_to_xe_bo(res->bo);
enum ttm_caching caching = ttm_cached;
u16 pat_index;
u32 ptes;
u64 ofs = (u64)at_pt * XE_PAGE_SIZE;
u64 cur_ofs;
/* Indirect access needs compression enabled uncached PAT index */
if (GRAPHICS_VERx100(xe) >= 2000)
pat_index = is_comp_pte ? xe_cache_pat_idx(xe, XE_CACHE_NONE_COMPRESSION) :
xe_cache_pat_idx(xe, XE_CACHE_WB);
else
pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
if (!is_vram && bo->ttm.ttm)
caching = bo->ttm.ttm->caching;
pat_index = xe_migrate_pat_index(xe, caching, is_comp_pte);
ptes = DIV_ROUND_UP(size, XE_PAGE_SIZE);