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drm/bridge: tc358767: Limit the Pixel PLL input range

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According to new configuration spreadsheet from Toshiba for TC9595,
the Pixel PLL input clock have to be in range 6..40 MHz. The sheet
calculates those PLL input clock as reference clock divided by both
pre-dividers. Add the extra limit.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240118220243.203655-1-marex@denx.de
This commit is contained in:
Marek Vasut
2024-01-18 23:02:31 +01:00
committed by Robert Foss
parent 71fc3249f5
commit f86ae204be
1 changed files with 6 additions and 1 deletions
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7
drivers/gpu/drm/bridge/tc358767.c
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@@ -617,9 +617,14 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
continue;
for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
for (div = 1; div <= 16; div++) {
u32 clk;
u32 clk, iclk;
u64 tmp;
/* PCLK PLL input unit clock ... 6..40 MHz */
iclk = refclk / (div * ext_div[i_pre]);
if (iclk < 6000000 || iclk > 40000000)
continue;
tmp = pixelclock * ext_div[i_pre] *
ext_div[i_post] * div;
do_div(tmp, refclk);