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spi: spi-qpic-snand: remove 'qpic_snand_op' structure

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The 'qpic_snand_op' structure is used only in the qcom_spi_send_cmdaddr()
function as a type of a local variable. Additionally, the sole purpose of
that variable is to keep some interim values before those gets passed as
arguments for cpu_to_le32() calls.

In order to simplify the code, remove the definition of the structure
along with the local variable, and use the corresponding values directly
as parameters for cpu_to_le32() calls.

No functional changes intended.

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://patch.msgid.link/20250529-qpic-snand-remove-qpic_snand_op-v1-1-6e42b772d748@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Gabor Juhos
2025-05-29 19:35:44 +02:00
committed by Mark Brown
parent 6c1ca9928e
commit f73dc37ebf
1 changed files with 9 additions and 26 deletions
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35
drivers/spi/spi-qpic-snand.c
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@@ -59,12 +59,6 @@
#define OOB_BUF_SIZE 128
#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
struct qpic_snand_op {
u32 cmd_reg;
u32 addr1_reg;
u32 addr2_reg;
};
struct snandc_read_status {
__le32 snandc_flash;
__le32 snandc_buffer;
@@ -1294,7 +1288,6 @@ static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
const struct spi_mem_op *op)
{
struct qpic_snand_op s_op = {};
u32 cmd;
int ret, opcode;
@@ -1302,34 +1295,24 @@ static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
if (ret < 0)
return ret;
s_op.cmd_reg = cmd;
s_op.addr1_reg = op->addr.val;
s_op.addr2_reg = 0;
opcode = op->cmd.opcode;
switch (opcode) {
case SPINAND_WRITE_EN:
return 0;
case SPINAND_PROGRAM_EXECUTE:
s_op.addr1_reg = op->addr.val << 16;
s_op.addr2_reg = op->addr.val >> 16 & 0xff;
snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff);
snandc->qspi->cmd = cpu_to_le32(cmd);
return qcom_spi_program_execute(snandc, op);
case SPINAND_READ:
s_op.addr1_reg = (op->addr.val << 16);
s_op.addr2_reg = op->addr.val >> 16 & 0xff;
snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff);
snandc->qspi->cmd = cpu_to_le32(cmd);
return 0;
case SPINAND_ERASE:
s_op.addr2_reg = (op->addr.val >> 16) & 0xffff;
s_op.addr1_reg = op->addr.val;
snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16);
snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xffff);
snandc->qspi->cmd = cpu_to_le32(cmd);
return qcom_spi_block_erase(snandc);
default:
@@ -1341,10 +1324,10 @@ static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
qcom_clear_read_regs(snandc);
qcom_clear_bam_transaction(snandc);
snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg);
snandc->regs->cmd = cpu_to_le32(cmd);
snandc->regs->exec = cpu_to_le32(1);
snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg);
snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg);
snandc->regs->addr0 = cpu_to_le32(op->addr.val);
snandc->regs->addr1 = cpu_to_le32(0);
qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);