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Merge tag 'samsung-dt64-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

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Samsung DTS ARM64 changes for v5.15

1. Add CPU topology and cache information to Exynos DTSI files.
2. Correct GIC CPU interfaces address range on Exynos7.

* tag 'samsung-dt64-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7
  arm64: dts: exynos: add CPU topology to Exynos5433
  arm64: dts: exynos: Add cpu cache information to Exynos5433
  arm64: dts: exynos: Add cpu cache information to Exynos7

Link: https://lore.kernel.org/r/20210811085128.30103-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2021-08-12 22:55:50 +02:00
parent 0b72a27e1d 01c72cad79
commit f73979109b
2 changed files with 138 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

102
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View File

@@ -52,6 +52,38 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
@@ -62,6 +94,13 @@ cpu0: cpu@100 {
clock-names = "apolloclk";
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&cluster_a53_l2>;
};
cpu1: cpu@101 {
@@ -72,6 +111,13 @@ cpu1: cpu@101 {
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&cluster_a53_l2>;
};
cpu2: cpu@102 {
@@ -82,6 +128,13 @@ cpu2: cpu@102 {
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&cluster_a53_l2>;
};
cpu3: cpu@103 {
@@ -92,6 +145,13 @@ cpu3: cpu@103 {
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&cluster_a53_l2>;
};
cpu4: cpu@0 {
@@ -104,6 +164,13 @@ cpu4: cpu@0 {
clock-names = "atlasclk";
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cluster_a57_l2>;
};
cpu5: cpu@1 {
@@ -114,6 +181,13 @@ cpu5: cpu@1 {
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cluster_a57_l2>;
};
cpu6: cpu@2 {
@@ -124,6 +198,13 @@ cpu6: cpu@2 {
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cluster_a57_l2>;
};
cpu7: cpu@3 {
@@ -134,6 +215,27 @@ cpu7: cpu@3 {
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cluster_a57_l2>;
};
cluster_a57_l2: l2-cache0 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
};
cluster_a53_l2: l2-cache1 {
compatible = "cache";
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
};
};

37
arch/arm64/boot/dts/exynos/exynos7.dtsi
View File

@@ -54,6 +54,13 @@ cpu_atlas0: cpu@0 {
compatible = "arm,cortex-a57";
reg = <0x0>;
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&atlas_l2>;
};
cpu_atlas1: cpu@1 {
@@ -61,6 +68,13 @@ cpu_atlas1: cpu@1 {
compatible = "arm,cortex-a57";
reg = <0x1>;
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&atlas_l2>;
};
cpu_atlas2: cpu@2 {
@@ -68,6 +82,13 @@ cpu_atlas2: cpu@2 {
compatible = "arm,cortex-a57";
reg = <0x2>;
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&atlas_l2>;
};
cpu_atlas3: cpu@3 {
@@ -75,6 +96,20 @@ cpu_atlas3: cpu@3 {
compatible = "arm,cortex-a57";
reg = <0x3>;
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&atlas_l2>;
};
atlas_l2: l2-cache0 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
};
};
@@ -102,7 +137,7 @@ gic: interrupt-controller@11001000 {
#address-cells = <0>;
interrupt-controller;
reg = <0x11001000 0x1000>,
<0x11002000 0x1000>,
<0x11002000 0x2000>,
<0x11004000 0x2000>,
<0x11006000 0x2000>;
};