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Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue

Browse Source 
Tony Nguyen says:

====================
Fix E825 initialization

Grzegorz Nitka says:

E825 products have incorrect initialization procedure, which may lead to
initialization failures and register values.

Fix E825 products initialization by adding correct sync delay, checking
the PHY revision only for current PHY and adding proper destination
device when reading port/quad.

In addition, E825 uses PF ID for indexing per PF registers and as
a primary PHY lane number, which is incorrect.

* '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue:
  ice: Add correct PHY lane assignment
  ice: Fix ETH56G FC-FEC Rx offset value
  ice: Fix quad registers read on E825
  ice: Fix E825 initialization
====================

Link: https://patch.msgid.link/20250113182840.3564250-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
2025-01-14 13:41:16 -08:00
parent 9de1280fb5 258f5f9058
commit f62bb88782
9 changed files with 209 additions and 144 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
View File

@@ -1665,6 +1665,7 @@ struct ice_aqc_get_port_options_elem {
#define ICE_AQC_PORT_OPT_MAX_LANE_25G 5
#define ICE_AQC_PORT_OPT_MAX_LANE_50G 6
#define ICE_AQC_PORT_OPT_MAX_LANE_100G 7
#define ICE_AQC_PORT_OPT_MAX_LANE_200G 8
u8 global_scid[2];
u8 phy_scid[2];

51
drivers/net/ethernet/intel/ice/ice_common.c
View File

@@ -4095,6 +4095,57 @@ ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
}
/**
* ice_get_phy_lane_number - Get PHY lane number for current adapter
* @hw: pointer to the hw struct
*
* Return: PHY lane number on success, negative error code otherwise.
*/
int ice_get_phy_lane_number(struct ice_hw *hw)
{
struct ice_aqc_get_port_options_elem *options;
unsigned int lport = 0;
unsigned int lane;
int err;
options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL);
if (!options)
return -ENOMEM;
for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) {
u8 options_count = ICE_AQC_PORT_OPT_MAX;
u8 speed, active_idx, pending_idx;
bool active_valid, pending_valid;
err = ice_aq_get_port_options(hw, options, &options_count, lane,
true, &active_idx, &active_valid,
&pending_idx, &pending_valid);
if (err)
goto err;
if (!active_valid)
continue;
speed = options[active_idx].max_lane_speed;
/* If we don't get speed for this lane, it's unoccupied */
if (speed > ICE_AQC_PORT_OPT_MAX_LANE_200G)
continue;
if (hw->pf_id == lport) {
kfree(options);
return lane;
}
lport++;
}
/* PHY lane not found */
err = -ENXIO;
err:
kfree(options);
return err;
}
/**
* ice_aq_sff_eeprom
* @hw: pointer to the HW struct

1
drivers/net/ethernet/intel/ice/ice_common.h
View File

@@ -193,6 +193,7 @@ ice_aq_get_port_options(struct ice_hw *hw,
int
ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
u8 new_option);
int ice_get_phy_lane_number(struct ice_hw *hw);
int
ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,

6
drivers/net/ethernet/intel/ice/ice_main.c
View File

@@ -1144,7 +1144,7 @@ ice_link_event(struct ice_pf *pf, struct ice_port_info *pi, bool link_up,
if (link_up == old_link && link_speed == old_link_speed)
return 0;
ice_ptp_link_change(pf, pf->hw.pf_id, link_up);
ice_ptp_link_change(pf, link_up);
if (ice_is_dcb_active(pf)) {
if (test_bit(ICE_FLAG_DCB_ENA, pf->flags))
@@ -6790,7 +6790,7 @@ static int ice_up_complete(struct ice_vsi *vsi)
ice_print_link_msg(vsi, true);
netif_tx_start_all_queues(vsi->netdev);
netif_carrier_on(vsi->netdev);
ice_ptp_link_change(pf, pf->hw.pf_id, true);
ice_ptp_link_change(pf, true);
}
/* Perform an initial read of the statistics registers now to
@@ -7260,7 +7260,7 @@ int ice_down(struct ice_vsi *vsi)
if (vsi->netdev) {
vlan_err = ice_vsi_del_vlan_zero(vsi);
ice_ptp_link_change(vsi->back, vsi->back->hw.pf_id, false);
ice_ptp_link_change(vsi->back, false);
netif_carrier_off(vsi->netdev);
netif_tx_disable(vsi->netdev);
}

23
drivers/net/ethernet/intel/ice/ice_ptp.c
View File

@@ -1388,10 +1388,9 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
/**
* ice_ptp_link_change - Reconfigure PTP after link status change
* @pf: Board private structure
* @port: Port for which the PHY start is set
* @linkup: Link is up or down
*/
void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
void ice_ptp_link_change(struct ice_pf *pf, bool linkup)
{
struct ice_ptp_port *ptp_port;
struct ice_hw *hw = &pf->hw;
@@ -1399,14 +1398,7 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
if (pf->ptp.state != ICE_PTP_READY)
return;
if (WARN_ON_ONCE(port >= hw->ptp.num_lports))
return;
ptp_port = &pf->ptp.port;
if (ice_is_e825c(hw) && hw->ptp.is_2x50g_muxed_topo)
port *= 2;
if (WARN_ON_ONCE(ptp_port->port_num != port))
return;
/* Update cached link status for this port immediately */
ptp_port->link_up = linkup;
@@ -3164,10 +3156,17 @@ void ice_ptp_init(struct ice_pf *pf)
{
struct ice_ptp *ptp = &pf->ptp;
struct ice_hw *hw = &pf->hw;
int err;
int lane_num, err;
ptp->state = ICE_PTP_INITIALIZING;
lane_num = ice_get_phy_lane_number(hw);
if (lane_num < 0) {
err = lane_num;
goto err_exit;
}
ptp->port.port_num = (u8)lane_num;
ice_ptp_init_hw(hw);
ice_ptp_init_tx_interrupt_mode(pf);
@@ -3188,10 +3187,6 @@ void ice_ptp_init(struct ice_pf *pf)
if (err)
goto err_exit;
ptp->port.port_num = hw->pf_id;
if (ice_is_e825c(hw) && hw->ptp.is_2x50g_muxed_topo)
ptp->port.port_num = hw->pf_id * 2;
err = ice_ptp_init_port(pf, &ptp->port);
if (err)
goto err_exit;

4
drivers/net/ethernet/intel/ice/ice_ptp.h
View File

@@ -310,7 +310,7 @@ void ice_ptp_prepare_for_reset(struct ice_pf *pf,
enum ice_reset_req reset_type);
void ice_ptp_init(struct ice_pf *pf);
void ice_ptp_release(struct ice_pf *pf);
void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup);
void ice_ptp_link_change(struct ice_pf *pf, bool linkup);
#else /* IS_ENABLED(CONFIG_PTP_1588_CLOCK) */
static inline int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)
{
@@ -358,7 +358,7 @@ static inline void ice_ptp_prepare_for_reset(struct ice_pf *pf,
}
static inline void ice_ptp_init(struct ice_pf *pf) { }
static inline void ice_ptp_release(struct ice_pf *pf) { }
static inline void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
static inline void ice_ptp_link_change(struct ice_pf *pf, bool linkup)
{
}

2
drivers/net/ethernet/intel/ice/ice_ptp_consts.h
View File

@@ -131,7 +131,7 @@ struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD] = {
.rx_offset = {
.serdes = 0xffffeb27, /* -10.42424 */
.no_fec = 0xffffcccd, /* -25.6 */
.fc = 0xfffe0014, /* -255.96 */
.fc = 0xfffc557b, /* -469.26 */
.sfd = 0x4a4, /* 2.32 */
.bs_ds = 0x32 /* 0.0969697 */
}

263
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
View File

@@ -900,31 +900,46 @@ static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
* The following functions operate on devices with the ETH 56G PHY.
*/
/**
* ice_ptp_get_dest_dev_e825 - get destination PHY for given port number
* @hw: pointer to the HW struct
* @port: destination port
*
* Return: destination sideband queue PHY device.
*/
static enum ice_sbq_msg_dev ice_ptp_get_dest_dev_e825(struct ice_hw *hw,
u8 port)
{
/* On a single complex E825, PHY 0 is always destination device phy_0
* and PHY 1 is phy_0_peer.
*/
if (port >= hw->ptp.ports_per_phy)
return eth56g_phy_1;
else
return eth56g_phy_0;
}
/**
* ice_write_phy_eth56g - Write a PHY port register
* @hw: pointer to the HW struct
* @phy_idx: PHY index
* @port: destination port
* @addr: PHY register address
* @val: Value to write
*
* Return: 0 on success, other error codes when failed to write to PHY
*/
static int ice_write_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr,
u32 val)
static int ice_write_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 val)
{
struct ice_sbq_msg_input phy_msg;
struct ice_sbq_msg_input msg = {
.dest_dev = ice_ptp_get_dest_dev_e825(hw, port),
.opcode = ice_sbq_msg_wr,
.msg_addr_low = lower_16_bits(addr),
.msg_addr_high = upper_16_bits(addr),
.data = val
};
int err;
phy_msg.opcode = ice_sbq_msg_wr;
phy_msg.msg_addr_low = lower_16_bits(addr);
phy_msg.msg_addr_high = upper_16_bits(addr);
phy_msg.data = val;
phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx];
err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD);
err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
if (err)
ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
err);
@@ -935,41 +950,36 @@ static int ice_write_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr,
/**
* ice_read_phy_eth56g - Read a PHY port register
* @hw: pointer to the HW struct
* @phy_idx: PHY index
* @port: destination port
* @addr: PHY register address
* @val: Value to write
*
* Return: 0 on success, other error codes when failed to read from PHY
*/
static int ice_read_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr,
u32 *val)
static int ice_read_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 *val)
{
struct ice_sbq_msg_input phy_msg;
struct ice_sbq_msg_input msg = {
.dest_dev = ice_ptp_get_dest_dev_e825(hw, port),
.opcode = ice_sbq_msg_rd,
.msg_addr_low = lower_16_bits(addr),
.msg_addr_high = upper_16_bits(addr)
};
int err;
phy_msg.opcode = ice_sbq_msg_rd;
phy_msg.msg_addr_low = lower_16_bits(addr);
phy_msg.msg_addr_high = upper_16_bits(addr);
phy_msg.data = 0;
phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx];
err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD);
if (err) {
err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
if (err)
ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
err);
return err;
}
else
*val = msg.data;
*val = phy_msg.data;
return 0;
return err;
}
/**
* ice_phy_res_address_eth56g - Calculate a PHY port register address
* @port: Port number to be written
* @hw: pointer to the HW struct
* @lane: Lane number to be written
* @res_type: resource type (register/memory)
* @offset: Offset from PHY port register base
* @addr: The result address
@@ -978,17 +988,19 @@ static int ice_read_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr,
* * %0 - success
* * %EINVAL - invalid port number or resource type
*/
static int ice_phy_res_address_eth56g(u8 port, enum eth56g_res_type res_type,
u32 offset, u32 *addr)
static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane,
enum eth56g_res_type res_type,
u32 offset,
u32 *addr)
{
u8 lane = port % ICE_PORTS_PER_QUAD;
u8 phy = ICE_GET_QUAD_NUM(port);
if (res_type >= NUM_ETH56G_PHY_RES)
return -EINVAL;
*addr = eth56g_phy_res[res_type].base[phy] +
/* Lanes 4..7 are in fact 0..3 on a second PHY */
lane %= hw->ptp.ports_per_phy;
*addr = eth56g_phy_res[res_type].base[0] +
lane * eth56g_phy_res[res_type].step + offset;
return 0;
}
@@ -1008,19 +1020,17 @@ static int ice_phy_res_address_eth56g(u8 port, enum eth56g_res_type res_type,
static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
u32 val, enum eth56g_res_type res_type)
{
u8 phy_port = port % hw->ptp.ports_per_phy;
u8 phy_idx = port / hw->ptp.ports_per_phy;
u32 addr;
int err;
if (port >= hw->ptp.num_lports)
return -EINVAL;
err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr);
err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr);
if (err)
return err;
return ice_write_phy_eth56g(hw, phy_idx, addr, val);
return ice_write_phy_eth56g(hw, port, addr, val);
}
/**
@@ -1039,19 +1049,17 @@ static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
u32 *val, enum eth56g_res_type res_type)
{
u8 phy_port = port % hw->ptp.ports_per_phy;
u8 phy_idx = port / hw->ptp.ports_per_phy;
u32 addr;
int err;
if (port >= hw->ptp.num_lports)
return -EINVAL;
err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr);
err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr);
if (err)
return err;
return ice_read_phy_eth56g(hw, phy_idx, addr, val);
return ice_read_phy_eth56g(hw, port, addr, val);
}
/**
@@ -1200,6 +1208,56 @@ static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset,
return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP);
}
/**
* ice_write_quad_ptp_reg_eth56g - Write a PHY quad register
* @hw: pointer to the HW struct
* @offset: PHY register offset
* @port: Port number
* @val: Value to write
*
* Return:
* * %0 - success
* * %EIO - invalid port number or resource type
* * %other - failed to write to PHY
*/
static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
u32 offset, u32 val)
{
u32 addr;
if (port >= hw->ptp.num_lports)
return -EIO;
addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset;
return ice_write_phy_eth56g(hw, port, addr, val);
}
/**
* ice_read_quad_ptp_reg_eth56g - Read a PHY quad register
* @hw: pointer to the HW struct
* @offset: PHY register offset
* @port: Port number
* @val: Value to read
*
* Return:
* * %0 - success
* * %EIO - invalid port number or resource type
* * %other - failed to read from PHY
*/
static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
u32 offset, u32 *val)
{
u32 addr;
if (port >= hw->ptp.num_lports)
return -EIO;
addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset;
return ice_read_phy_eth56g(hw, port, addr, val);
}
/**
* ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register
* @low_addr: the low address to check
@@ -1919,7 +1977,6 @@ ice_phy_get_speed_eth56g(struct ice_link_status *li)
*/
static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port)
{
u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
u32 val;
int err;
@@ -1934,8 +1991,8 @@ static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port)
switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) {
case ICE_ETH56G_LNK_SPD_1G:
case ICE_ETH56G_LNK_SPD_2_5G:
err = ice_read_ptp_reg_eth56g(hw, port_blk,
PHY_GPCS_CONFIG_REG0, &val);
err = ice_read_quad_ptp_reg_eth56g(hw, port,
PHY_GPCS_CONFIG_REG0, &val);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d",
err);
@@ -1946,8 +2003,8 @@ static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port)
val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M,
ICE_ETH56G_NOMINAL_TX_THRESH);
err = ice_write_ptp_reg_eth56g(hw, port_blk,
PHY_GPCS_CONFIG_REG0, val);
err = ice_write_quad_ptp_reg_eth56g(hw, port,
PHY_GPCS_CONFIG_REG0, val);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d",
err);
@@ -1988,50 +2045,47 @@ static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port)
*/
int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port)
{
u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
u8 blk_port = port & (ICE_PORTS_PER_QUAD - 1);
u8 quad_lane = port % ICE_PORTS_PER_QUAD;
u32 addr, val, peer_delay;
bool enable, sfd_ena;
u32 val, peer_delay;
int err;
enable = hw->ptp.phy.eth56g.onestep_ena;
peer_delay = hw->ptp.phy.eth56g.peer_delay;
sfd_ena = hw->ptp.phy.eth56g.sfd_ena;
/* PHY_PTP_1STEP_CONFIG */
err = ice_read_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, &val);
addr = PHY_PTP_1STEP_CONFIG;
err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &val);
if (err)
return err;
if (enable)
val |= blk_port;
val |= BIT(quad_lane);
else
val &= ~blk_port;
val &= ~BIT(quad_lane);
val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M);
err = ice_write_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, val);
err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val);
if (err)
return err;
/* PHY_PTP_1STEP_PEER_DELAY */
addr = PHY_PTP_1STEP_PEER_DELAY(quad_lane);
val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay);
if (peer_delay)
val |= PHY_PTP_1STEP_PD_ADD_PD_M;
val |= PHY_PTP_1STEP_PD_DLY_V_M;
err = ice_write_ptp_reg_eth56g(hw, port_blk,
PHY_PTP_1STEP_PEER_DELAY(blk_port), val);
err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val);
if (err)
return err;
val &= ~PHY_PTP_1STEP_PD_DLY_V_M;
err = ice_write_ptp_reg_eth56g(hw, port_blk,
PHY_PTP_1STEP_PEER_DELAY(blk_port), val);
err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val);
if (err)
return err;
/* PHY_MAC_XIF_MODE */
err = ice_read_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, &val);
addr = PHY_MAC_XIF_MODE;
err = ice_read_mac_reg_eth56g(hw, port, addr, &val);
if (err)
return err;
@@ -2051,7 +2105,7 @@ int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port)
FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) |
FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena);
return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, val);
return ice_write_mac_reg_eth56g(hw, port, addr, val);
}
/**
@@ -2093,21 +2147,22 @@ static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs,
bool fc, bool rs,
enum ice_eth56g_link_spd spd)
{
u8 port_offset = port & (ICE_PORTS_PER_QUAD - 1);
u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
u32 bitslip;
int err;
if (!bs || rs)
return 0;
if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G)
if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G) {
err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP,
&bitslip);
else
err = ice_read_ptp_reg_eth56g(hw, port_blk,
PHY_REG_SD_BIT_SLIP(port_offset),
&bitslip);
} else {
u8 quad_lane = port % ICE_PORTS_PER_QUAD;
u32 addr;
addr = PHY_REG_SD_BIT_SLIP(quad_lane);
err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &bitslip);
}
if (err)
return 0;
@@ -2667,59 +2722,29 @@ static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port,
}
/**
* ice_is_muxed_topo - detect breakout 2x50G topology for E825C
* @hw: pointer to the HW struct
*
* Return: true if it's 2x50 breakout topology, false otherwise
*/
static bool ice_is_muxed_topo(struct ice_hw *hw)
{
u8 link_topo;
bool mux;
u32 val;
val = rd32(hw, GLGEN_SWITCH_MODE_CONFIG);
mux = FIELD_GET(GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M, val);
val = rd32(hw, GLGEN_MAC_LINK_TOPO);
link_topo = FIELD_GET(GLGEN_MAC_LINK_TOPO_LINK_TOPO_M, val);
return (mux && link_topo == ICE_LINK_TOPO_UP_TO_2_LINKS);
}
/**
* ice_ptp_init_phy_e825c - initialize PHY parameters
* ice_ptp_init_phy_e825 - initialize PHY parameters
* @hw: pointer to the HW struct
*/
static void ice_ptp_init_phy_e825c(struct ice_hw *hw)
static void ice_ptp_init_phy_e825(struct ice_hw *hw)
{
struct ice_ptp_hw *ptp = &hw->ptp;
struct ice_eth56g_params *params;
u8 phy;
u32 phy_rev;
int err;
ptp->phy_model = ICE_PHY_ETH56G;
params = &ptp->phy.eth56g;
params->onestep_ena = false;
params->peer_delay = 0;
params->sfd_ena = false;
params->phy_addr[0] = eth56g_phy_0;
params->phy_addr[1] = eth56g_phy_1;
params->num_phys = 2;
ptp->ports_per_phy = 4;
ptp->num_lports = params->num_phys * ptp->ports_per_phy;
ice_sb_access_ena_eth56g(hw, true);
for (phy = 0; phy < params->num_phys; phy++) {
u32 phy_rev;
int err;
err = ice_read_phy_eth56g(hw, phy, PHY_REG_REVISION, &phy_rev);
if (err || phy_rev != PHY_REVISION_ETH56G) {
ptp->phy_model = ICE_PHY_UNSUP;
return;
}
}
ptp->is_2x50g_muxed_topo = ice_is_muxed_topo(hw);
err = ice_read_phy_eth56g(hw, hw->pf_id, PHY_REG_REVISION, &phy_rev);
if (err || phy_rev != PHY_REVISION_ETH56G)
ptp->phy_model = ICE_PHY_UNSUP;
}
/* E822 family functions
@@ -2738,10 +2763,9 @@ static void ice_fill_phy_msg_e82x(struct ice_hw *hw,
struct ice_sbq_msg_input *msg, u8 port,
u16 offset)
{
int phy_port, phy, quadtype;
int phy_port, quadtype;
phy_port = port % hw->ptp.ports_per_phy;
phy = port / hw->ptp.ports_per_phy;
quadtype = ICE_GET_QUAD_NUM(port) %
ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy);
@@ -2753,12 +2777,7 @@ static void ice_fill_phy_msg_e82x(struct ice_hw *hw,
msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port);
}
if (phy == 0)
msg->dest_dev = rmn_0;
else if (phy == 1)
msg->dest_dev = rmn_1;
else
msg->dest_dev = rmn_2;
msg->dest_dev = rmn_0;
}
/**
@@ -5478,7 +5497,7 @@ void ice_ptp_init_hw(struct ice_hw *hw)
else if (ice_is_e810(hw))
ice_ptp_init_phy_e810(ptp);
else if (ice_is_e825c(hw))
ice_ptp_init_phy_e825c(hw);
ice_ptp_init_phy_e825(hw);
else
ptp->phy_model = ICE_PHY_UNSUP;
}

2
drivers/net/ethernet/intel/ice/ice_type.h
View File

@@ -850,7 +850,6 @@ struct ice_mbx_data {
struct ice_eth56g_params {
u8 num_phys;
u8 phy_addr[2];
bool onestep_ena;
bool sfd_ena;
u32 peer_delay;
@@ -881,7 +880,6 @@ struct ice_ptp_hw {
union ice_phy_params phy;
u8 num_lports;
u8 ports_per_phy;
bool is_2x50g_muxed_topo;
};
/* Port hardware description */