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Merge tag 'drm-misc-next-fixes-2026-06-05' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next

Browse Source 
drm-misc-next-fixes for v7.2-rc1:
- Revert last minute IS_ERR_OR_NULL changes in nouveau/gsp.
- Fix build warning in drm scheduler.
- Flush caches and TLB before v3d runtime suspend.
- Fix a trace and debug command in amdxdna.
- Fix heap buffer address validation when PASID is disabled in amdxdna.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patch.msgid.link/a4a5bf50-3fc8-4faf-884b-08121687124a@linux.intel.com
This commit is contained in:
Dave Airlie
2026-06-09 15:00:01 +10:00
parent 5ea194bc25 62c1671f64
commit f5ed9dba31
10 changed files with 50 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/accel/amdxdna/aie2_ctx.c
View File

@@ -305,17 +305,13 @@ aie2_sched_drvcmd_resp_handler(void *handle, void __iomem *data, size_t size)
struct amdxdna_sched_job *job = handle;
int ret = 0;
if (unlikely(!data))
goto out;
if (unlikely(size != sizeof(u32))) {
if (unlikely(!data || size != sizeof(u32))) {
job->drv_cmd->result = U32_MAX;
ret = -EINVAL;
goto out;
} else {
job->drv_cmd->result = readl(data);
}
job->drv_cmd->result = readl(data);
out:
aie2_sched_notify(job);
return ret;
}
@@ -437,8 +433,9 @@ static void aie2_sched_job_free(struct drm_sched_job *sched_job)
struct amdxdna_sched_job *job = drm_job_to_xdna_job(sched_job);
struct amdxdna_hwctx *hwctx = job->hwctx;
/* job->drv_cmd could be freed, so use DEFAULT_IO */
trace_xdna_job(sched_job, hwctx->name, "job free",
job->seq, job->drv_cmd ? job->drv_cmd->opcode : DEFAULT_IO);
job->seq, DEFAULT_IO);
if (!job->job_done)
up(&hwctx->priv->job_sem);
@@ -939,6 +936,7 @@ static int aie2_hwctx_cfg_debug_bo(struct amdxdna_hwctx *hwctx, u32 bo_hdl,
aie2_cmd_wait(hwctx, seq);
if (cmd.result) {
XDNA_ERR(xdna, "Response failure 0x%x", cmd.result);
ret = -EINVAL;
goto put_obj;
}

5
drivers/accel/amdxdna/amdxdna_gem.c
View File

@@ -349,8 +349,11 @@ static int amdxdna_hmm_register(struct amdxdna_gem_obj *abo,
u32 nr_pages;
int ret;
if (!amdxdna_pasid_on(abo->client))
if (!amdxdna_pasid_on(abo->client)) {
/* Need to set uva for heap uva validation */
abo->mem.uva = addr;
return 0;
}
mapp = kzalloc_obj(*mapp);
if (!mapp)

8
drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
View File

@@ -293,7 +293,7 @@ nvkm_gsp_rpc_rd(struct nvkm_gsp *gsp, u32 fn, u32 argc)
{
void *argv = nvkm_gsp_rpc_get(gsp, fn, argc);
if (IS_ERR(argv))
if (IS_ERR_OR_NULL(argv))
return argv;
return nvkm_gsp_rpc_push(gsp, argv, NVKM_GSP_RPC_REPLY_RECV, argc);
@@ -373,7 +373,7 @@ nvkm_gsp_rm_alloc_get(struct nvkm_gsp_object *parent, u32 handle, u32 oclass, u3
object->handle = handle;
argv = gsp->rm->api->alloc->get(object, oclass, argc);
if (IS_ERR(argv)) {
if (IS_ERR_OR_NULL(argv)) {
object->client = NULL;
return argv;
}
@@ -415,8 +415,8 @@ nvkm_gsp_rm_alloc(struct nvkm_gsp_object *parent, u32 handle, u32 oclass, u32 ar
{
void *argv = nvkm_gsp_rm_alloc_get(parent, handle, oclass, argc, object);
if (IS_ERR(argv))
return PTR_ERR(argv);
if (IS_ERR_OR_NULL(argv))
return argv ? PTR_ERR(argv) : -EIO;
return nvkm_gsp_rm_alloc_wr(object, argv);
}

4
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/alloc.c
View File

@@ -35,7 +35,7 @@ r535_gsp_rpc_rm_free(struct nvkm_gsp_object *object)
client->object.handle, object->handle);
rpc = nvkm_gsp_rpc_get(gsp, NV_VGPU_MSG_FUNCTION_FREE, sizeof(*rpc));
if (WARN_ON(IS_ERR(rpc)))
if (WARN_ON(IS_ERR_OR_NULL(rpc)))
return -EIO;
rpc->params.hRoot = client->object.handle;
@@ -60,7 +60,7 @@ r535_gsp_rpc_rm_alloc_push(struct nvkm_gsp_object *object, void *params)
void *ret = NULL;
rpc = nvkm_gsp_rpc_push(gsp, rpc, NVKM_GSP_RPC_REPLY_RECV, sizeof(*rpc));
if (IS_ERR(rpc))
if (IS_ERR_OR_NULL(rpc))
return rpc;
if (rpc->status) {

2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/bar.c
View File

@@ -55,7 +55,7 @@ r535_bar_bar2_update_pde(struct nvkm_gsp *gsp, u8 page_shift, u64 pdbe)
rpc_update_bar_pde_v15_00 *rpc;
rpc = nvkm_gsp_rpc_get(gsp, NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE, sizeof(*rpc));
if (WARN_ON(IS_ERR(rpc)))
if (WARN_ON(IS_ERR_OR_NULL(rpc)))
return -EIO;
rpc->info.barType = NV_RPC_UPDATE_PDE_BAR_2;

2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/ctrl.c
View File

@@ -42,7 +42,7 @@ r535_gsp_rpc_rm_ctrl_push(struct nvkm_gsp_object *object, void **params, u32 rep
int ret = 0;
rpc = nvkm_gsp_rpc_push(gsp, rpc, NVKM_GSP_RPC_REPLY_RECV, repc);
if (IS_ERR(rpc)) {
if (IS_ERR_OR_NULL(rpc)) {
*params = NULL;
return PTR_ERR(rpc);
}

10
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c
View File

@@ -324,7 +324,7 @@ r535_gsp_msgq_recv(struct nvkm_gsp *gsp, u32 gsp_rpc_len, int *retries)
u32 size;
rpc = r535_gsp_msgq_peek(gsp, sizeof(*rpc), info.retries);
if (IS_ERR(rpc)) {
if (IS_ERR_OR_NULL(rpc)) {
kvfree(buf);
return rpc;
}
@@ -333,7 +333,7 @@ r535_gsp_msgq_recv(struct nvkm_gsp *gsp, u32 gsp_rpc_len, int *retries)
info.continuation = true;
rpc = r535_gsp_msgq_recv_one_elem(gsp, &info);
if (IS_ERR(rpc)) {
if (IS_ERR_OR_NULL(rpc)) {
kvfree(buf);
return rpc;
}
@@ -459,11 +459,11 @@ r535_gsp_msg_recv(struct nvkm_gsp *gsp, int fn, u32 gsp_rpc_len)
retry:
rpc = r535_gsp_msgq_peek(gsp, sizeof(*rpc), &retries);
if (IS_ERR(rpc))
if (IS_ERR_OR_NULL(rpc))
return rpc;
rpc = r535_gsp_msgq_recv(gsp, gsp_rpc_len, &retries);
if (IS_ERR(rpc))
if (IS_ERR_OR_NULL(rpc))
return rpc;
if (rpc->rpc_result) {
@@ -561,7 +561,7 @@ r535_gsp_rpc_handle_reply(struct nvkm_gsp *gsp, u32 fn,
break;
case NVKM_GSP_RPC_REPLY_RECV:
reply = r535_gsp_msg_recv(gsp, fn, gsp_rpc_len);
if (!IS_ERR(reply))
if (!IS_ERR_OR_NULL(reply))
repv = reply->data;
else
repv = reply;

12
drivers/gpu/drm/scheduler/tests/tests_scheduler.c
View File

@@ -666,14 +666,10 @@ static void drm_sched_scheduler_two_clients_test(struct kunit *test)
}
}
static const struct kunit_attributes drm_sched_scheduler_two_clients_attr = {
.speed = KUNIT_SPEED_SLOW,
};
static struct kunit_case drm_sched_scheduler_two_clients_tests[] = {
KUNIT_CASE_PARAM_ATTR(drm_sched_scheduler_two_clients_test,
drm_sched_scheduler_two_clients_gen_params,
drm_sched_scheduler_two_clients_attr),
{ .speed = KUNIT_SPEED_SLOW }),
{}
};
@@ -858,14 +854,10 @@ static void drm_sched_scheduler_many_clients_test(struct kunit *test)
drm_mock_sched_entity_free(client[i].entity);
}
static const struct kunit_attributes drm_sched_scheduler_many_clients_attr = {
.speed = KUNIT_SPEED_SLOW,
};
static struct kunit_case drm_sched_scheduler_many_clients_tests[] = {
KUNIT_CASE_PARAM_ATTR(drm_sched_scheduler_many_clients_test,
drm_sched_scheduler_many_clients_gen_params,
drm_sched_scheduler_many_clients_attr),
{ .speed = KUNIT_SPEED_SLOW }),
{}
};

31
drivers/gpu/drm/v3d/v3d_mmu.c
View File

@@ -37,13 +37,14 @@ static bool v3d_mmu_is_aligned(u32 page, u32 page_address, size_t alignment)
IS_ALIGNED(page_address, alignment >> V3D_MMU_PAGE_SHIFT);
}
int v3d_mmu_flush_all(struct v3d_dev *v3d)
/*
* Issue the MMUC flush and TLB clear unconditionally. The caller must
* already know that V3D is reachable. In particular, this is used from
* the runtime resume callback.
*/
static int v3d_mmu_flush_all_locked(struct v3d_dev *v3d)
{
int ret = 0;
/* Flush the PTs only if we're already awake */
if (!pm_runtime_get_if_active(v3d->drm.dev))
return 0;
int ret;
V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_FLUSH |
V3D_MMUC_CONTROL_ENABLE);
@@ -52,7 +53,7 @@ int v3d_mmu_flush_all(struct v3d_dev *v3d)
V3D_MMUC_CONTROL_FLUSHING), 100);
if (ret) {
dev_err(v3d->drm.dev, "MMUC flush wait idle failed\n");
goto pm_put;
return ret;
}
V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL) |
@@ -63,7 +64,19 @@ int v3d_mmu_flush_all(struct v3d_dev *v3d)
if (ret)
dev_err(v3d->drm.dev, "MMU TLB clear wait idle failed\n");
pm_put:
return ret;
}
int v3d_mmu_flush_all(struct v3d_dev *v3d)
{
int ret;
/* Flush the PTs only if we're already awake */
if (!pm_runtime_get_if_active(v3d->drm.dev))
return 0;
ret = v3d_mmu_flush_all_locked(v3d);
v3d_pm_runtime_put(v3d);
return ret;
}
@@ -85,7 +98,7 @@ int v3d_mmu_set_page_table(struct v3d_dev *v3d)
V3D_MMU_ILLEGAL_ADDR_ENABLE);
V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_ENABLE);
return v3d_mmu_flush_all(v3d);
return v3d_mmu_flush_all_locked(v3d);
}
void v3d_mmu_insert_ptes(struct v3d_bo *bo)

2
drivers/gpu/drm/v3d/v3d_power.c
View File

@@ -52,6 +52,8 @@ int v3d_power_suspend(struct device *dev)
v3d_irq_disable(v3d);
v3d_clean_caches(v3d);
ret = v3d_suspend_sms(v3d);
if (ret) {
v3d_irq_enable(v3d);