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arm64: dts: qcom: sm6115: align mem timer size cells with bindings

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Commit 70d1e09ebf ("arm64: dts: qcom: sm6115: Use 64 bit addressing")
converted all addresses to 64-bit addressing, but the ARMv7 memory
mapped architected timer bindings expect sizes up to 32-bit.  Keep
64-bit addressing but change size of memory mapping to 32-bit
(size-cells=1) and adjust the ranges to match this.

This fixes dtbs_check warnings like:

  sm6115p-lenovo-j606f.dtb: timer@f120000: #size-cells:0:0: 1 was expected

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231111164229.63803-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
2023-11-11 17:42:27 +01:00
committed by Bjorn Andersson
parent af6f6778d3
commit f52f11271d
1 changed files with 9 additions and 9 deletions
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18
arch/arm64/boot/dts/qcom/sm6115.dtsi
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@@ -2596,54 +2596,54 @@ timer@f120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x0f120000 0x0 0x1000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x0 0x20000000>;
clock-frequency = <19200000>;
frame@f121000 {
reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>;
reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>;
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
frame@f123000 {
reg = <0x0 0x0f123000 0x0 0x1000>;
reg = <0x0 0x0f123000 0x1000>;
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f124000 {
reg = <0x0 0x0f124000 0x0 0x1000>;
reg = <0x0 0x0f124000 0x1000>;
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f125000 {
reg = <0x0 0x0f125000 0x0 0x1000>;
reg = <0x0 0x0f125000 0x1000>;
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f126000 {
reg = <0x0 0x0f126000 0x0 0x1000>;
reg = <0x0 0x0f126000 0x1000>;
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f127000 {
reg = <0x0 0x0f127000 0x0 0x1000>;
reg = <0x0 0x0f127000 0x1000>;
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f128000 {
reg = <0x0 0x0f128000 0x0 0x1000>;
reg = <0x0 0x0f128000 0x1000>;
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";