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Merge tag 'perf-tools-for-v6.17-2025-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools

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Pull perf tools updates from Namhyung Kim:
 "Build-ID processing goodies:

     Build-IDs are content based hashes to link regions of memory to ELF
     files in post processing. They have been available in distros for
     quite a while:

       $ file /bin/bash
       /bin/bash: ELF 64-bit LSB pie executable, x86-64, version 1 (SYSV),
       dynamically linked, interpreter /lib64/ld-linux-x86-64.so.2,
       BuildID[sha1]=707a1c670cd72f8e55ffedfbe94ea98901b7ce3a,
       for GNU/Linux 3.2.0, stripped

     It is possible to ask the kernel to get it from mmap executable
     backing storage at time they are being put in place and send it as
     metadata at that moment to have in perf.data.

     Prefer that across the board to speed up 'record' time - it post
     processes the samples to find binaries touched by any samples and
     to save them with build-ID. It can skip reading build-ID in
     userspace if it comes from the kernel.

  perf record:

   * Make --buildid-mmap default.  The kernel can generate MMAP2 events
     with a build-ID from ELF header.  Use that by default instead of using
     inode and device ID to identify binaries.  It also can be disabled
     with --no-buildid-mmap.

   * Use BPF for -u/--uid option to sample processes belong to a user.
     BPF can track user processes more accurately and the existing logic
     often fails to get the list of processes due to race with reading the
     /proc filesystem.

   * Generate PERF_RECORD_BPF_METADATA when it profiles BPF programs and
     they have variables starting with "bpf_metadata_".  This will help to
     identify BPF objects used in the profile.  This has been supported in
     bpftool for some time and allows the recording of metadata such as
     commit hashes, versions, etc, that now gets recorded in perf.data as
     well.

   * Collect list of DSOs touched in the sample callchains as well as in
     the sample itself.  This would increase the processing time at the end
     of record, but can improve the data quality.

  perf stat:

   * Add a new 'drm' pseudo-PMU support like in 'hwmon'.  It can collect
     DRM usage stats using fdinfo in /proc.

     On my Intel laptop, it shows like below:

       $ perf list drm
       ...

       drm:
         drm-active-stolen-system0
              [Total memory active in one or more engines. Unit: drm_i915]
         drm-active-system0
              [Total memory active in one or more engines. Unit: drm_i915]
         drm-engine-capacity-video
              [Engine capacity. Unit: drm_i915]
         drm-engine-copy
              [Utilization in ns. Unit: drm_i915]
         drm-engine-render
              [Utilization in ns. Unit: drm_i915]
         drm-engine-video
              [Utilization in ns. Unit: drm_i915]
         ...

       $ sudo perf stat -a -e drm-engine-render,drm-engine-video,drm-engine-capacity-video sleep 1

        Performance counter stats for 'system wide':

       48,137,316,988,873 ns       drm-engine-render
           34,452,696,746 ns       drm-engine-video
                       20 capacity drm-engine-capacity-video

              1.002086194 seconds time elapsed

  perf list

   * Add description for software events.  The description is in JSON format
     and the event parser now can handle the software events like others
     (for example, it's case-insensitive and subject to wildcard matching).

       $ perf list software

       List of pre-defined events (to be used in -e or -M):

       software:
         alignment-faults
              [Number of kernel handled memory alignment faults. Unit: software]
         bpf-output
              [An event used by BPF programs to write to the perf ring buffer. Unit: software]
         cgroup-switches
              [Number of context switches to a task in a different cgroup. Unit: software]
         context-switches
              [Number of context switches [This event is an alias of cs]. Unit: software]
         cpu-clock
              [Per-CPU high-resolution timer based event. Unit: software]
         cpu-migrations
              [Number of times a process has migrated to a new CPU [This event is an alias of migrations]. Unit: software]
         cs
              [Number of context switches [This event is an alias of context-switches]. Unit: software]
         dummy
              [A placeholder event that doesn't count anything. Unit: software]
         emulation-faults
              [Number of kernel handled unimplemented instruction faults handled through emulation. Unit: software]
         faults
              [Number of page faults [This event is an alias of page-faults]. Unit: software]
         major-faults
              [Number of major page faults. Major faults require I/O to handle. Unit: software]
         migrations
              [Number of times a process has migrated to a new CPU [This event is an alias of cpu-migrations]. Unit: software]
         minor-faults
              [Number of minor page faults. Minor faults don't require I/O to handle. Unit: software]
         page-faults
              [Number of page faults [This event is an alias of faults]. Unit: software]
         task-clock
              [Per-task high-resolution timer based event. Unit: software]

  perf ftrace:

   * Add -e/--events option to perf ftrace latency to measure latency
     between the two events instead of a function.

       $ sudo perf ftrace latency -ab -e i915_request_wait_begin,i915_request_wait_end --hide-empty -- sleep 1
       #   DURATION     |      COUNT | GRAPH                                |
          256 -  512 us |          4 | ######                               |
            2 -    4 ms |          2 | ###                                  |
            4 -    8 ms |         12 | ###################                  |
            8 -   16 ms |         10 | ################                     |

       # statistics  (in usec)
         total time:               194915
           avg time:                 6961
           max time:                12855
           min time:                  373
              count:                   28

   * Add new function graph tracer options (--graph-opts) to display more
     info like arguments and return value.  They will be passed to the
     kernel ftrace directly.

       $ sudo perf ftrace -G vfs_write --graph-opts retval,retaddr
       # tracer: function_graph
       #
       # CPU  DURATION                  FUNCTION CALLS
       # |     |   |                     |   |   |   |
       ...
       5)               |  mutex_unlock() { /* <-rb_simple_write+0xda/0x150 */
       5)   0.188 us    |    local_clock(); /* <-lock_release+0x2ad/0x440 ret=0x3bf2a3cf90e */
       5)               |    rt_mutex_slowunlock() { /* <-rb_simple_write+0xda/0x150 */
       5)               |      _raw_spin_lock_irqsave() { /* <-rt_mutex_slowunlock+0x4f/0x200 */
       5)   0.123 us    |        preempt_count_add(); /* <-_raw_spin_lock_irqsave+0x23/0x90 ret=0x0 */
       5)   0.128 us    |        local_clock(); /* <-__lock_acquire.isra.0+0x17a/0x740 ret=0x3bf2a3cfc8b */
       5)   0.086 us    |        do_raw_spin_trylock(); /* <-_raw_spin_lock_irqsave+0x4a/0x90 ret=0x1 */
       5)   0.845 us    |      } /* _raw_spin_lock_irqsave ret=0x292 */
       ...

  Misc:

   * Add perf archive --exclude-buildids <FILE> option to skip some binaries.
     The format of the FILE should be same as an output of perf buildid-list.

   * Get rid of dependency of libcrypto.  It was just to get SHA-1 hash so
     implement it directly like in the kernel.  A side effect is that it
     needs -fno-strict-aliasing compiler option (again, like in the kernel).

   * Convert all shell script tests to use bash"

* tag 'perf-tools-for-v6.17-2025-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools: (179 commits)
  perf record: Cache build-ID of hit DSOs only
  perf test: Ensure lock contention using pipe mode
  perf python: Stop using deprecated PyUnicode_AsString()
  perf list: Skip ABI PMUs when printing pmu values
  perf list: Remove tracepoint printing code
  perf tp_pmu: Add event APIs
  perf tp_pmu: Factor existing tracepoint logic to new file
  perf parse-events: Remove non-json software events
  perf jevents: Add common software event json
  perf tools: Remove libtraceevent in .gitignore
  perf test: Fix comment ordering
  perf sort: Use perf_env to set arch sort keys and header
  perf test: Move PERF_SAMPLE_WEIGHT_STRUCT parsing to common test
  perf sample: Remove arch notion of sample parsing
  perf env: Remove global perf_env
  perf trace: Avoid global perf_env with evsel__env
  perf auxtrace: Pass perf_env from session through to mmap read
  perf machine: Explicitly pass in host perf_env
  perf bench synthesize: Avoid use of global perf_env
  perf top: Make perf_env locally scoped
  ...
This commit is contained in:
Linus Torvalds
2025-08-01 16:55:47 -07:00
parent 0905809b38 6235ce7774
commit f4f346c346
359 changed files with 10633 additions and 3345 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
tools/build/Makefile.feature
View File

@@ -86,7 +86,6 @@ FEATURE_TESTS_BASIC := \
libtraceevent \
libtracefs \
libcpupower \
libcrypto \
pthread-attr-setaffinity-np \
pthread-barrier \
reallocarray \
@@ -126,12 +125,7 @@ FEATURE_TESTS_EXTRA := \
llvm \
clang \
libbpf \
libbpf-btf__load_from_kernel_by_id \
libbpf-bpf_prog_load \
libbpf-bpf_object__next_program \
libbpf-bpf_object__next_map \
libbpf-bpf_program__set_insns \
libbpf-bpf_create_map \
libbpf-strings \
libpfm4 \
libdebuginfod \
clang-bpf-co-re \
@@ -152,7 +146,6 @@ FEATURE_DISPLAY ?= \
numa_num_possible_cpus \
libperl \
libpython \
libcrypto \
libcapstone \
llvm-perf \
zlib \

27
tools/build/feature/Makefile
View File

@@ -38,7 +38,6 @@ FILES= \
test-libtraceevent.bin \
test-libcpupower.bin \
test-libtracefs.bin \
test-libcrypto.bin \
test-libunwind.bin \
test-libunwind-debug-frame.bin \
test-libunwind-x86.bin \
@@ -59,6 +58,7 @@ FILES= \
test-lzma.bin \
test-bpf.bin \
test-libbpf.bin \
test-libbpf-strings.bin \
test-get_cpuid.bin \
test-sdt.bin \
test-cxx.bin \
@@ -246,9 +246,6 @@ $(OUTPUT)test-libcpupower.bin:
$(OUTPUT)test-libtracefs.bin:
$(BUILD) $(shell $(PKG_CONFIG) --cflags libtracefs 2>/dev/null) -ltracefs
$(OUTPUT)test-libcrypto.bin:
$(BUILD) -lcrypto
$(OUTPUT)test-gtk2.bin:
$(BUILD) $(shell $(PKG_CONFIG) --libs --cflags gtk+-2.0 2>/dev/null) -Wno-deprecated-declarations
@@ -339,26 +336,8 @@ $(OUTPUT)test-bpf.bin:
$(OUTPUT)test-libbpf.bin:
$(BUILD) -lbpf
$(OUTPUT)test-libbpf-btf__load_from_kernel_by_id.bin:
$(BUILD) -lbpf
$(OUTPUT)test-libbpf-bpf_prog_load.bin:
$(BUILD) -lbpf
$(OUTPUT)test-libbpf-bpf_map_create.bin:
$(BUILD) -lbpf
$(OUTPUT)test-libbpf-bpf_object__next_program.bin:
$(BUILD) -lbpf
$(OUTPUT)test-libbpf-bpf_object__next_map.bin:
$(BUILD) -lbpf
$(OUTPUT)test-libbpf-bpf_program__set_insns.bin:
$(BUILD) -lbpf
$(OUTPUT)test-libbpf-btf__raw_data.bin:
$(BUILD) -lbpf
$(OUTPUT)test-libbpf-strings.bin:
$(BUILD)
$(OUTPUT)test-sdt.bin:
$(BUILD)

24
tools/build/feature/test-all.c
View File

@@ -66,14 +66,6 @@
# include "test-libslang.c"
#undef main
#define main main_test_libbfd
# include "test-libbfd.c"
#undef main
#define main main_test_libbfd_buildid
# include "test-libbfd-buildid.c"
#undef main
#define main main_test_backtrace
# include "test-backtrace.c"
#undef main
@@ -138,10 +130,6 @@
# include "test-bpf.c"
#undef main
#define main main_test_libcrypto
# include "test-libcrypto.c"
#undef main
#define main main_test_sdt
# include "test-sdt.c"
#undef main
@@ -158,14 +146,6 @@
# include "test-reallocarray.c"
#undef main
#define main main_test_disassembler_four_args
# include "test-disassembler-four-args.c"
#undef main
#define main main_test_disassembler_init_styled
# include "test-disassembler-init-styled.c"
#undef main
#define main main_test_libzstd
# include "test-libzstd.c"
#undef main
@@ -193,8 +173,6 @@ int main(int argc, char *argv[])
main_test_libelf_gelf_getnote();
main_test_libelf_getshdrstrndx();
main_test_libslang();
main_test_libbfd();
main_test_libbfd_buildid();
main_test_backtrace();
main_test_libnuma();
main_test_numa_num_possible_cpus();
@@ -206,14 +184,12 @@ int main(int argc, char *argv[])
main_test_lzma();
main_test_get_cpuid();
main_test_bpf();
main_test_libcrypto();
main_test_scandirat();
main_test_sched_getcpu();
main_test_sdt();
main_test_setns();
main_test_libaio();
main_test_reallocarray();
main_test_disassembler_four_args();
main_test_libzstd();
main_test_libtraceevent();
main_test_libtracefs();

10
tools/build/feature/test-libbpf-strings.c Normal file
View File

@@ -0,0 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
#include <bpf/btf.h>
int main(void)
{
struct btf_dump_type_data_opts opts;
opts.emit_strings = 0;
return opts.emit_strings;
}

25
tools/build/feature/test-libcrypto.c
View File

@@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include <openssl/evp.h>
#include <openssl/sha.h>
#include <openssl/md5.h>
int main(void)
{
EVP_MD_CTX *mdctx;
unsigned char md[MD5_DIGEST_LENGTH + SHA_DIGEST_LENGTH];
unsigned char dat[] = "12345";
unsigned int digest_len;
mdctx = EVP_MD_CTX_new();
if (!mdctx)
return 0;
EVP_DigestInit_ex(mdctx, EVP_md5(), NULL);
EVP_DigestUpdate(mdctx, &dat[0], sizeof(dat));
EVP_DigestFinal_ex(mdctx, &md[0], &digest_len);
EVP_MD_CTX_free(mdctx);
SHA1(&dat[0], sizeof(dat), &md[0]);
return 0;
}

123
tools/lib/perf/evlist.c
View File

@@ -36,49 +36,88 @@ void perf_evlist__init(struct perf_evlist *evlist)
static void __perf_evlist__propagate_maps(struct perf_evlist *evlist,
struct perf_evsel *evsel)
{
if (evsel->system_wide) {
/* System wide: set the cpu map of the evsel to all online CPUs. */
perf_cpu_map__put(evsel->cpus);
evsel->cpus = perf_cpu_map__new_online_cpus();
} else if (evlist->has_user_cpus && evsel->is_pmu_core) {
/*
* User requested CPUs on a core PMU, ensure the requested CPUs
* are valid by intersecting with those of the PMU.
*/
perf_cpu_map__put(evsel->cpus);
evsel->cpus = perf_cpu_map__intersect(evlist->user_requested_cpus, evsel->own_cpus);
/*
* Empty cpu lists would eventually get opened as "any" so remove
* genuinely empty ones before they're opened in the wrong place.
*/
if (perf_cpu_map__is_empty(evsel->cpus)) {
struct perf_evsel *next = perf_evlist__next(evlist, evsel);
perf_evlist__remove(evlist, evsel);
/* Keep idx contiguous */
if (next)
list_for_each_entry_from(next, &evlist->entries, node)
next->idx--;
if (perf_cpu_map__is_empty(evsel->cpus)) {
if (perf_cpu_map__is_empty(evsel->pmu_cpus)) {
/*
* Assume the unset PMU cpus were for a system-wide
* event, like a software or tracepoint.
*/
evsel->pmu_cpus = perf_cpu_map__new_online_cpus();
}
} else if (!evsel->own_cpus || evlist->has_user_cpus ||
(!evsel->requires_cpu && perf_cpu_map__has_any_cpu(evlist->user_requested_cpus))) {
/*
* The PMU didn't specify a default cpu map, this isn't a core
* event and the user requested CPUs or the evlist user
* requested CPUs have the "any CPU" (aka dummy) CPU value. In
* which case use the user requested CPUs rather than the PMU
* ones.
*/
if (evlist->has_user_cpus && !evsel->system_wide) {
/*
* Use the user CPUs unless the evsel is set to be
* system wide, such as the dummy event.
*/
evsel->cpus = perf_cpu_map__get(evlist->user_requested_cpus);
} else {
/*
* System wide and other modes, assume the cpu map
* should be set to all PMU CPUs.
*/
evsel->cpus = perf_cpu_map__get(evsel->pmu_cpus);
}
}
/*
* Avoid "any CPU"(-1) for uncore and PMUs that require a CPU, even if
* requested.
*/
if (evsel->requires_cpu && perf_cpu_map__has_any_cpu(evsel->cpus)) {
perf_cpu_map__put(evsel->cpus);
evsel->cpus = perf_cpu_map__get(evsel->pmu_cpus);
}
/*
* Globally requested CPUs replace user requested unless the evsel is
* set to be system wide.
*/
if (evlist->has_user_cpus && !evsel->system_wide) {
assert(!perf_cpu_map__has_any_cpu(evlist->user_requested_cpus));
if (!perf_cpu_map__equal(evsel->cpus, evlist->user_requested_cpus)) {
perf_cpu_map__put(evsel->cpus);
evsel->cpus = perf_cpu_map__get(evlist->user_requested_cpus);
}
}
/* Ensure cpus only references valid PMU CPUs. */
if (!perf_cpu_map__has_any_cpu(evsel->cpus) &&
!perf_cpu_map__is_subset(evsel->pmu_cpus, evsel->cpus)) {
struct perf_cpu_map *tmp = perf_cpu_map__intersect(evsel->pmu_cpus, evsel->cpus);
perf_cpu_map__put(evsel->cpus);
evsel->cpus = tmp;
}
/*
* Was event requested on all the PMU's CPUs but the user requested is
* any CPU (-1)? If so switch to using any CPU (-1) to reduce the number
* of events.
*/
if (!evsel->system_wide &&
!evsel->requires_cpu &&
perf_cpu_map__equal(evsel->cpus, evsel->pmu_cpus) &&
perf_cpu_map__has_any_cpu(evlist->user_requested_cpus)) {
perf_cpu_map__put(evsel->cpus);
evsel->cpus = perf_cpu_map__get(evlist->user_requested_cpus);
} else if (evsel->cpus != evsel->own_cpus) {
/*
* No user requested cpu map but the PMU cpu map doesn't match
* the evsel's. Reset it back to the PMU cpu map.
*/
perf_cpu_map__put(evsel->cpus);
evsel->cpus = perf_cpu_map__get(evsel->own_cpus);
}
/* Sanity check assert before the evsel is potentially removed. */
assert(!evsel->requires_cpu || !perf_cpu_map__has_any_cpu(evsel->cpus));
/*
* Empty cpu lists would eventually get opened as "any" so remove
* genuinely empty ones before they're opened in the wrong place.
*/
if (perf_cpu_map__is_empty(evsel->cpus)) {
struct perf_evsel *next = perf_evlist__next(evlist, evsel);
perf_evlist__remove(evlist, evsel);
/* Keep idx contiguous */
if (next)
list_for_each_entry_from(next, &evlist->entries, node)
next->idx--;
return;
}
if (evsel->system_wide) {
@@ -98,6 +137,10 @@ static void perf_evlist__propagate_maps(struct perf_evlist *evlist)
evlist->needs_map_propagation = true;
/* Clear the all_cpus set which will be merged into during propagation. */
perf_cpu_map__put(evlist->all_cpus);
evlist->all_cpus = NULL;
list_for_each_entry_safe(evsel, n, &evlist->entries, node)
__perf_evlist__propagate_maps(evlist, evsel);
}

11
tools/lib/perf/evsel.c
View File

@@ -40,8 +40,19 @@ struct perf_evsel *perf_evsel__new(struct perf_event_attr *attr)
return evsel;
}
void perf_evsel__exit(struct perf_evsel *evsel)
{
assert(evsel->fd == NULL); /* If not fds were not closed. */
assert(evsel->mmap == NULL); /* If not munmap wasn't called. */
assert(evsel->sample_id == NULL); /* If not free_id wasn't called. */
perf_cpu_map__put(evsel->cpus);
perf_cpu_map__put(evsel->pmu_cpus);
perf_thread_map__put(evsel->threads);
}
void perf_evsel__delete(struct perf_evsel *evsel)
{
perf_evsel__exit(evsel);
free(evsel);
}

3
tools/lib/perf/include/internal/evsel.h
View File

@@ -99,7 +99,7 @@ struct perf_evsel {
* cpu map for opening the event on, for example, the first CPU on a
* socket for an uncore event.
*/
struct perf_cpu_map *own_cpus;
struct perf_cpu_map *pmu_cpus;
struct perf_thread_map *threads;
struct xyarray *fd;
struct xyarray *mmap;
@@ -133,6 +133,7 @@ struct perf_evsel {
void perf_evsel__init(struct perf_evsel *evsel, struct perf_event_attr *attr,
int idx);
void perf_evsel__exit(struct perf_evsel *evsel);
int perf_evsel__alloc_fd(struct perf_evsel *evsel, int ncpus, int nthreads);
void perf_evsel__close_fd(struct perf_evsel *evsel);
void perf_evsel__free_fd(struct perf_evsel *evsel);

18
tools/lib/perf/include/perf/event.h
View File

@@ -467,6 +467,22 @@ struct perf_record_compressed2 {
char data[];
};
#define BPF_METADATA_KEY_LEN 64
#define BPF_METADATA_VALUE_LEN 256
#define BPF_PROG_NAME_LEN KSYM_NAME_LEN
struct perf_record_bpf_metadata_entry {
char key[BPF_METADATA_KEY_LEN];
char value[BPF_METADATA_VALUE_LEN];
};
struct perf_record_bpf_metadata {
struct perf_event_header header;
char prog_name[BPF_PROG_NAME_LEN];
__u64 nr_entries;
struct perf_record_bpf_metadata_entry entries[];
};
enum perf_user_event_type { /* above any possible kernel type */
PERF_RECORD_USER_TYPE_START = 64,
PERF_RECORD_HEADER_ATTR = 64,
@@ -489,6 +505,7 @@ enum perf_user_event_type { /* above any possible kernel type */
PERF_RECORD_COMPRESSED = 81,
PERF_RECORD_FINISHED_INIT = 82,
PERF_RECORD_COMPRESSED2 = 83,
PERF_RECORD_BPF_METADATA = 84,
PERF_RECORD_HEADER_MAX
};
@@ -530,6 +547,7 @@ union perf_event {
struct perf_record_header_feature feat;
struct perf_record_compressed pack;
struct perf_record_compressed2 pack2;
struct perf_record_bpf_metadata bpf_metadata;
};
#endif /* __LIBPERF_EVENT_H */

12
tools/lib/subcmd/help.c
View File

@@ -9,6 +9,7 @@
#include <sys/stat.h>
#include <unistd.h>
#include <dirent.h>
#include <assert.h>
#include "subcmd-util.h"
#include "help.h"
#include "exec-cmd.h"
@@ -82,10 +83,11 @@ void exclude_cmds(struct cmdnames *cmds, struct cmdnames *excludes)
ci++;
cj++;
} else {
zfree(&cmds->names[cj]);
cmds->names[cj++] = cmds->names[ci++];
cmds->names[cj++] = cmds->names[ci];
cmds->names[ci++] = NULL;
}
} else if (cmp == 0) {
zfree(&cmds->names[ci]);
ci++;
ei++;
} else if (cmp > 0) {
@@ -94,12 +96,12 @@ void exclude_cmds(struct cmdnames *cmds, struct cmdnames *excludes)
}
if (ci != cj) {
while (ci < cmds->cnt) {
zfree(&cmds->names[cj]);
cmds->names[cj++] = cmds->names[ci++];
cmds->names[cj++] = cmds->names[ci];
cmds->names[ci++] = NULL;
}
}
for (ci = cj; ci < cmds->cnt; ci++)
zfree(&cmds->names[ci]);
assert(cmds->names[ci] == NULL);
cmds->cnt = cj;
}

15
tools/lib/subcmd/run-command.c
View File

@@ -5,6 +5,7 @@
#include <ctype.h>
#include <fcntl.h>
#include <string.h>
#include <linux/compiler.h>
#include <linux/string.h>
#include <errno.h>
#include <sys/wait.h>
@@ -216,10 +217,20 @@ static int wait_or_whine(struct child_process *cmd, bool block)
return result;
}
/*
* Conservative estimate of number of characaters needed to hold an a decoded
* integer, assume each 3 bits needs a character byte and plus a possible sign
* character.
*/
#ifndef is_signed_type
#define is_signed_type(type) (((type)(-1)) < (type)1)
#endif
#define MAX_STRLEN_TYPE(type) (sizeof(type) * 8 / 3 + (is_signed_type(type) ? 1 : 0))
int check_if_command_finished(struct child_process *cmd)
{
#ifdef __linux__
char filename[FILENAME_MAX + 12];
char filename[6 + MAX_STRLEN_TYPE(typeof(cmd->pid)) + 7 + 1];
char status_line[256];
FILE *status_file;
@@ -227,7 +238,7 @@ int check_if_command_finished(struct child_process *cmd)
* Check by reading /proc/<pid>/status as calling waitpid causes
* stdout/stderr to be closed and data lost.
*/
sprintf(filename, "/proc/%d/status", cmd->pid);
sprintf(filename, "/proc/%u/status", cmd->pid);
status_file = fopen(filename, "r");
if (status_file == NULL) {
/* Open failed assume finish_command was called. */

2
tools/perf/.gitignore vendored
View File

@@ -48,8 +48,6 @@ libbpf/
libperf/
libsubcmd/
libsymbol/
libtraceevent/
libtraceevent_plugins/
fixdep
Documentation/doc.dep
python_ext_build/

2
tools/perf/Build
View File

@@ -73,7 +73,7 @@ endif
$(OUTPUT)%.shellcheck_log: %
$(call rule_mkdir)
$(Q)$(call echo-cmd,test)shellcheck -s bash -a -S warning "$<" > $@ || (cat $@ && rm $@ && false)
$(Q)$(call echo-cmd,test)$(SHELLCHECK) "$<" > $@ || (cat $@ && rm $@ && false)
perf-y += $(SHELL_TEST_LOGS)

2
tools/perf/Documentation/perf-check.txt
View File

@@ -52,8 +52,8 @@ feature::
dwarf-unwind / HAVE_DWARF_UNWIND_SUPPORT
auxtrace / HAVE_AUXTRACE_SUPPORT
libbfd / HAVE_LIBBFD_SUPPORT
libbpf-strings / HAVE_LIBBPF_STRINGS_SUPPORT
libcapstone / HAVE_LIBCAPSTONE_SUPPORT
libcrypto / HAVE_LIBCRYPTO_SUPPORT
libdw-dwarf-unwind / HAVE_LIBDW_SUPPORT
libelf / HAVE_LIBELF_SUPPORT
libnuma / HAVE_LIBNUMA_SUPPORT

10
tools/perf/Documentation/perf-ftrace.txt
View File

@@ -123,6 +123,10 @@ OPTIONS for 'perf ftrace trace'
--graph-opts::
List of options allowed to set:
- args - Show function arguments.
- retval - Show function return value.
- retval-hex - Show function return value in hexadecimal format.
- retaddr - Show function return address.
- nosleep-time - Measure on-CPU time only for function_graph tracer.
- noirqs - Ignore functions that happen inside interrupt.
- verbose - Show process names, PIDs, timestamps, etc.
@@ -139,6 +143,12 @@ OPTIONS for 'perf ftrace latency'
Set the function name to get the histogram. Unlike perf ftrace trace,
it only allows single function to calculate the histogram.
-e::
--events=::
Set the pair of events to get the histogram. The histogram is calculated
by the time difference between the two events from the same thread. This
requires -b/--use-bpf option.
-b::
--use-bpf::
Use BPF to measure function latency instead of using the ftrace (it

25
tools/perf/Documentation/perf-list.txt
View File

@@ -278,26 +278,33 @@ also be supplied. For example:
perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
EVENT QUALIFIERS:
EVENT QUALIFIERS
----------------
It is also possible to add extra qualifiers to an event:
percore:
Sums up the event counts for all hardware threads in a core, e.g.:
perf stat -e cpu/event=0,umask=0x3,percore=1/
Sums up the event counts for all hardware threads in a core, e.g.:
perf stat -e cpu/event=0,umask=0x3,percore=1/
cpu:
Specifies the CPU to open the event upon. The value may be repeated to
specify opening the event on multiple CPUs:
Specifies a CPU or a range of CPUs to open the event upon. It may
also reference a PMU to copy the CPU mask from. The value may be
repeated to specify opening the event on multiple CPUs.
Example 1: to open the instructions event on CPUs 0 and 2, the
cycles event on CPUs 1 and 2:
perf stat -e instructions/cpu=0,cpu=2/,cycles/cpu=1-2/ -a sleep 1
perf stat -e instructions/cpu=0,cpu=2/,cycles/cpu=1,cpu=2/ -a sleep 1
perf stat -e data_read/cpu=0/,data_write/cpu=1/ -a sleep 1
Example 2: to open the data_read uncore event on CPU 0 and the
data_write uncore event on CPU 1:
perf stat -e data_read/cpu=0/,data_write/cpu=1/ -a sleep 1
Example 3: to open the software msr/tsc/ event only on the CPUs
matching those from the cpu_core PMU:
perf stat -e msr/tsc,cpu=cpu_core/ -a sleep 1
EVENT GROUPS
------------

4
tools/perf/Documentation/perf-record.txt
View File

@@ -563,7 +563,9 @@ Specify vmlinux path which has debuginfo.
Record build-id of all DSOs regardless whether it's actually hit or not.
--buildid-mmap::
Record build ids in mmap2 events, disables build id cache (implies --no-buildid).
Legacy record build-id in map events option which is now the
default. Behaves indentically to --no-buildid. Disable with
--no-buildid-mmap.
--aio[=n]::
Use <n> control blocks in asynchronous (Posix AIO) trace writing mode (default: 1, max: 4).

6
tools/perf/Documentation/perf-stat.txt
View File

@@ -640,18 +640,20 @@ JSON FORMAT
With -j, perf stat is able to print out a JSON format output
that can be used for parsing.
- timestamp : optional usec time stamp in fractions of second (with -I)
- interval : optional timestamp in fractions of second (with -I)
- optional aggregate options:
- core : core identifier (with --per-core)
- die : die identifier (with --per-die)
- socket : socket identifier (with --per-socket)
- node : node identifier (with --per-node)
- thread : thread identifier (with --per-thread)
- counters : number of aggregated PMU counters
- counter-value : counter value
- unit : unit of the counter value or empty
- event : event name
- variance : optional variance if multiple values are collected (with -r)
- runtime : run time of counter
- event-runtime : run time of the event
- pcnt-running : percentage of time the event was running
- metric-value : optional metric value
- metric-unit : optional unit of metric

8
tools/perf/Documentation/perf-trace.txt
View File

@@ -238,14 +238,6 @@ the thread executes on the designated CPUs. Default is to monitor all CPUs.
the same beautifiers used in the strace-like enter+exit lines to augment the
tracepoint arguments.
--map-dump::
Dump BPF maps setup by events passed via -e, for instance the augmented_raw_syscalls
living in tools/perf/examples/bpf/augmented_raw_syscalls.c. For now this
dumps just boolean map values and integer keys, in time this will print in hex
by default and use BTF when available, as well as use functions to do pretty
printing using the existing 'perf trace' syscall arg beautifiers to map integer
arguments to strings (pid to comm, syscall id to syscall name, etc).
--force-btf::
Use btf_dump to pretty print syscall argument data, instead of using hand-crafted pretty
printers. This option is intended for testing BTF integration in perf trace. btf_dump-based

34
tools/perf/Makefile.config
View File

@@ -19,6 +19,10 @@ detected_var = $(shell echo "$(1)=$($(1))" >> $(OUTPUT).config-detected)
CFLAGS := $(EXTRA_CFLAGS) $(filter-out -Wnested-externs,$(EXTRA_WARNINGS))
HOSTCFLAGS := $(filter-out -Wnested-externs,$(EXTRA_WARNINGS))
# This is required because the kernel is built with this and some of the code
# borrowed from kernel headers depends on it, e.g. put_unaligned_*().
CFLAGS += -fno-strict-aliasing
# Enabled Wthread-safety analysis for clang builds.
ifeq ($(CC_NO_CLANG), 0)
CFLAGS += -Wthread-safety
@@ -130,8 +134,6 @@ ifndef NO_LIBUNWIND
FEATURE_CHECK_LDFLAGS-libunwind-x86_64 += -lunwind -llzma -lunwind-x86_64
endif
FEATURE_CHECK_LDFLAGS-libcrypto = -lcrypto
ifdef CSINCLUDES
LIBOPENCSD_CFLAGS := -I$(CSINCLUDES)
endif
@@ -595,8 +597,16 @@ ifndef NO_LIBELF
LIBBPF_STATIC := 1
$(call detected,CONFIG_LIBBPF)
CFLAGS += -DHAVE_LIBBPF_SUPPORT
LIBBPF_INCLUDE = $(LIBBPF_DIR)/..
endif
endif
FEATURE_CHECK_CFLAGS-libbpf-strings="-I$(LIBBPF_INCLUDE)"
$(call feature_check,libbpf-strings)
ifeq ($(feature-libbpf-strings), 1)
$(call detected,CONFIG_LIBBPF_STRINGS)
CFLAGS += -DHAVE_LIBBPF_STRINGS_SUPPORT
endif
endif
endif # NO_LIBBPF
endif # NO_LIBELF
@@ -772,17 +782,6 @@ ifneq ($(NO_LIBTRACEEVENT),1)
$(call detected,CONFIG_TRACE)
endif
ifndef NO_LIBCRYPTO
ifneq ($(feature-libcrypto), 1)
$(warning No libcrypto.h found, disables jitted code injection, please install openssl-devel or libssl-dev)
NO_LIBCRYPTO := 1
else
CFLAGS += -DHAVE_LIBCRYPTO_SUPPORT
EXTLIBS += -lcrypto
$(call detected,CONFIG_CRYPTO)
endif
endif
ifndef NO_SLANG
ifneq ($(feature-libslang), 1)
ifneq ($(feature-libslang-include-subdir), 1)
@@ -918,6 +917,8 @@ ifneq ($(NO_JEVENTS),1)
endif
ifdef BUILD_NONDISTRO
$(call feature_check,libbfd)
ifeq ($(feature-libbfd), 1)
EXTLIBS += -lbfd -lopcodes
else
@@ -946,6 +947,9 @@ ifdef BUILD_NONDISTRO
CFLAGS += -DHAVE_LIBBFD_SUPPORT
CXXFLAGS += -DHAVE_LIBBFD_SUPPORT
$(call feature_check,libbfd-buildid)
ifeq ($(feature-libbfd-buildid), 1)
CFLAGS += -DHAVE_LIBBFD_BUILDID_SUPPORT
else
@@ -1144,7 +1148,7 @@ ifndef NO_JVMTI
endif
endif # NO_JVMTI_CMLR
else
$(warning No openjdk development package found, please install JDK package, e.g. openjdk-8-jdk, java-1.8.0-openjdk-devel)
$(warning No openjdk development package found, please install JDK package, e.g. openjdk-8-jdk, java-latest-openjdk-devel)
NO_JVMTI := 1
endif
endif
@@ -1157,7 +1161,7 @@ ifndef NO_LIBPFM4
ASCIIDOC_EXTRA = -aHAVE_LIBPFM=1
$(call detected,CONFIG_LIBPFM4)
else
$(warning libpfm4 not found, disables libpfm4 support. Please install libpfm4-dev)
$(warning libpfm4 not found, disables libpfm4 support. Please install libpfm-devel or libpfm4-dev)
endif
endif

12
tools/perf/Makefile.perf
View File

@@ -61,9 +61,6 @@ include ../scripts/utilities.mak
#
# Define NO_LIBBIONIC if you do not want bionic support
#
# Define NO_LIBCRYPTO if you do not want libcrypto (openssl) support
# used for generating build-ids for ELFs generated by jitdump.
#
# Define NO_LIBDW_DWARF_UNWIND if you do not want libdw support
# for dwarf backtrace post unwind.
#
@@ -262,6 +259,8 @@ ifneq ($(SHELLCHECK),)
ifeq ($(shell expr $(shell $(SHELLCHECK) --version | grep version: | \
sed -e 's/.\+ \([0-9]\+\).\([0-9]\+\).\([0-9]\+\)/\1\2\3/g') \< 060), 1)
SHELLCHECK :=
else
SHELLCHECK := $(SHELLCHECK) -s bash -a -S warning
endif
endif
@@ -1250,8 +1249,11 @@ else
$(Q)cp "$(VMLINUX_H)" $@
endif
$(SKEL_TMP_OUT)/%.bpf.o: util/bpf_skel/%.bpf.c $(LIBBPF) $(SKEL_OUT)/vmlinux.h | $(SKEL_TMP_OUT)
$(QUIET_CLANG)$(CLANG) -g -O2 --target=bpf $(CLANG_OPTIONS) $(BPF_INCLUDE) $(TOOLS_UAPI_INCLUDE) \
$(SKEL_TMP_OUT)/%.bpf.o: $(OUTPUT)PERF-VERSION-FILE util/bpf_skel/perf_version.h | $(SKEL_TMP_OUT)
$(SKEL_TMP_OUT)/%.bpf.o: util/bpf_skel/%.bpf.c $(LIBBPF) $(SKEL_OUT)/vmlinux.h
$(QUIET_CLANG)$(CLANG) -g -O2 -fno-stack-protector --target=bpf \
$(CLANG_OPTIONS) $(BPF_INCLUDE) $(TOOLS_UAPI_INCLUDE) \
-include $(OUTPUT)PERF-VERSION-FILE -include util/bpf_skel/perf_version.h \
-c $(filter util/bpf_skel/%.bpf.c,$^) -o $@
$(SKEL_OUT)/%.skel.h: $(SKEL_TMP_OUT)/%.bpf.o | $(BPFTOOL)

1
tools/perf/arch/powerpc/util/Build
View File

@@ -5,7 +5,6 @@ perf-util-y += mem-events.o
perf-util-y += pmu.o
perf-util-y += sym-handling.o
perf-util-y += evsel.o
perf-util-y += event.o
perf-util-$(CONFIG_LIBDW) += skip-callchain-idx.o

60
tools/perf/arch/powerpc/util/event.c
View File

@@ -1,60 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/types.h>
#include <linux/string.h>
#include <linux/zalloc.h>
#include "../../../util/event.h"
#include "../../../util/synthetic-events.h"
#include "../../../util/machine.h"
#include "../../../util/tool.h"
#include "../../../util/map.h"
#include "../../../util/debug.h"
#include "../../../util/sample.h"
void arch_perf_parse_sample_weight(struct perf_sample *data,
const __u64 *array, u64 type)
{
union perf_sample_weight weight;
weight.full = *array;
if (type & PERF_SAMPLE_WEIGHT)
data->weight = weight.full;
else {
data->weight = weight.var1_dw;
data->ins_lat = weight.var2_w;
data->p_stage_cyc = weight.var3_w;
}
}
void arch_perf_synthesize_sample_weight(const struct perf_sample *data,
__u64 *array, u64 type)
{
*array = data->weight;
if (type & PERF_SAMPLE_WEIGHT_STRUCT) {
*array &= 0xffffffff;
*array |= ((u64)data->ins_lat << 32);
}
}
const char *arch_perf_header_entry(const char *se_header)
{
if (!strcmp(se_header, "Local INSTR Latency"))
return "Finish Cyc";
else if (!strcmp(se_header, "INSTR Latency"))
return "Global Finish_cyc";
else if (!strcmp(se_header, "Local Pipeline Stage Cycle"))
return "Dispatch Cyc";
else if (!strcmp(se_header, "Pipeline Stage Cycle"))
return "Global Dispatch_cyc";
return se_header;
}
int arch_support_sort_key(const char *sort_key)
{
if (!strcmp(sort_key, "p_stage_cyc"))
return 1;
if (!strcmp(sort_key, "local_p_stage_cyc"))
return 1;
return 0;
}

2
tools/perf/arch/x86/Build
View File

@@ -10,6 +10,6 @@ endif
$(OUTPUT)%.shellcheck_log: %
$(call rule_mkdir)
$(Q)$(call echo-cmd,test)shellcheck -a -S warning "$<" > $@ || (cat $@ && rm $@ && false)
$(Q)$(call echo-cmd,test)$(SHELLCHECK) "$<" > $@ || (cat $@ && rm $@ && false)
perf-test-y += $(SHELL_TEST_LOGS)

5
tools/perf/arch/x86/include/arch-tests.h
View File

@@ -2,6 +2,8 @@
#ifndef ARCH_TESTS_H
#define ARCH_TESTS_H
#include "tests/tests.h"
struct test_suite;
/* Tests */
@@ -12,11 +14,12 @@ int test__insn_x86(struct test_suite *test, int subtest);
int test__intel_pt_pkt_decoder(struct test_suite *test, int subtest);
int test__intel_pt_hybrid_compat(struct test_suite *test, int subtest);
int test__bp_modify(struct test_suite *test, int subtest);
int test__x86_sample_parsing(struct test_suite *test, int subtest);
int test__amd_ibs_via_core_pmu(struct test_suite *test, int subtest);
int test__amd_ibs_period(struct test_suite *test, int subtest);
int test__hybrid(struct test_suite *test, int subtest);
DECLARE_SUITE(x86_topdown);
extern struct test_suite *arch_tests[];
#endif

4
tools/perf/arch/x86/tests/Build
View File

@@ -2,7 +2,6 @@ perf-test-$(CONFIG_DWARF_UNWIND) += regs_load.o
perf-test-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o
perf-test-y += arch-tests.o
perf-test-y += sample-parsing.o
perf-test-y += hybrid.o
perf-test-$(CONFIG_AUXTRACE) += intel-pt-test.o
ifeq ($(CONFIG_EXTRA_TESTS),y)
@@ -11,6 +10,7 @@ endif
perf-test-$(CONFIG_X86_64) += bp-modify.o
perf-test-y += amd-ibs-via-core-pmu.o
perf-test-y += amd-ibs-period.o
perf-test-y += topdown.o
ifdef SHELLCHECK
SHELL_TESTS := gen-insn-x86-dat.sh
@@ -22,6 +22,6 @@ endif
$(OUTPUT)%.shellcheck_log: %
$(call rule_mkdir)
$(Q)$(call echo-cmd,test)shellcheck -a -S warning "$<" > $@ || (cat $@ && rm $@ && false)
$(Q)$(call echo-cmd,test)$(SHELLCHECK) "$<" > $@ || (cat $@ && rm $@ && false)
perf-test-y += $(SHELL_TEST_LOGS)

3
tools/perf/arch/x86/tests/arch-tests.c
View File

@@ -23,7 +23,6 @@ struct test_suite suite__intel_pt = {
#if defined(__x86_64__)
DEFINE_SUITE("x86 bp modify", bp_modify);
#endif
DEFINE_SUITE("x86 Sample parsing", x86_sample_parsing);
DEFINE_SUITE("AMD IBS via core pmu", amd_ibs_via_core_pmu);
DEFINE_SUITE_EXCLUSIVE("AMD IBS sample period", amd_ibs_period);
static struct test_case hybrid_tests[] = {
@@ -49,9 +48,9 @@ struct test_suite *arch_tests[] = {
#if defined(__x86_64__)
&suite__bp_modify,
#endif
&suite__x86_sample_parsing,
&suite__amd_ibs_via_core_pmu,
&suite__amd_ibs_period,
&suite__hybrid,
&suite__x86_topdown,
NULL,
};

125
tools/perf/arch/x86/tests/sample-parsing.c
View File

@@ -1,125 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <stdbool.h>
#include <inttypes.h>
#include <stdlib.h>
#include <string.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include "event.h"
#include "evsel.h"
#include "debug.h"
#include "util/sample.h"
#include "util/synthetic-events.h"
#include "tests/tests.h"
#include "arch-tests.h"
#define COMP(m) do { \
if (s1->m != s2->m) { \
pr_debug("Samples differ at '"#m"'\n"); \
return false; \
} \
} while (0)
static bool samples_same(const struct perf_sample *s1,
const struct perf_sample *s2,
u64 type)
{
if (type & PERF_SAMPLE_WEIGHT_STRUCT) {
COMP(ins_lat);
COMP(retire_lat);
}
return true;
}
static int do_test(u64 sample_type)
{
struct evsel evsel = {
.needs_swap = false,
.core = {
. attr = {
.sample_type = sample_type,
.read_format = 0,
},
},
};
union perf_event *event;
struct perf_sample sample = {
.weight = 101,
.ins_lat = 102,
.retire_lat = 103,
};
struct perf_sample sample_out;
size_t i, sz, bufsz;
int err, ret = -1;
sz = perf_event__sample_event_size(&sample, sample_type, 0);
bufsz = sz + 4096; /* Add a bit for overrun checking */
event = malloc(bufsz);
if (!event) {
pr_debug("malloc failed\n");
return -1;
}
memset(event, 0xff, bufsz);
event->header.type = PERF_RECORD_SAMPLE;
event->header.misc = 0;
event->header.size = sz;
err = perf_event__synthesize_sample(event, sample_type, 0, &sample);
if (err) {
pr_debug("%s failed for sample_type %#"PRIx64", error %d\n",
"perf_event__synthesize_sample", sample_type, err);
goto out_free;
}
/* The data does not contain 0xff so we use that to check the size */
for (i = bufsz; i > 0; i--) {
if (*(i - 1 + (u8 *)event) != 0xff)
break;
}
if (i != sz) {
pr_debug("Event size mismatch: actual %zu vs expected %zu\n",
i, sz);
goto out_free;
}
evsel.sample_size = __evsel__sample_size(sample_type);
err = evsel__parse_sample(&evsel, event, &sample_out);
if (err) {
pr_debug("%s failed for sample_type %#"PRIx64", error %d\n",
"evsel__parse_sample", sample_type, err);
goto out_free;
}
if (!samples_same(&sample, &sample_out, sample_type)) {
pr_debug("parsing failed for sample_type %#"PRIx64"\n",
sample_type);
goto out_free;
}
ret = 0;
out_free:
free(event);
return ret;
}
/**
* test__x86_sample_parsing - test X86 specific sample parsing
*
* This function implements a test that synthesizes a sample event, parses it
* and then checks that the parsed sample matches the original sample. If the
* test passes %0 is returned, otherwise %-1 is returned.
*
* For now, the PERF_SAMPLE_WEIGHT_STRUCT is the only X86 specific sample type.
* The test only checks the PERF_SAMPLE_WEIGHT_STRUCT type.
*/
int test__x86_sample_parsing(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
return do_test(PERF_SAMPLE_WEIGHT_STRUCT);
}

76
tools/perf/arch/x86/tests/topdown.c Normal file
View File

@@ -0,0 +1,76 @@
// SPDX-License-Identifier: GPL-2.0
#include "arch-tests.h"
#include "../util/topdown.h"
#include "evlist.h"
#include "parse-events.h"
#include "pmu.h"
#include "pmus.h"
static int event_cb(void *state, struct pmu_event_info *info)
{
char buf[256];
struct parse_events_error parse_err;
int *ret = state, err;
struct evlist *evlist = evlist__new();
struct evsel *evsel;
if (!evlist)
return -ENOMEM;
parse_events_error__init(&parse_err);
snprintf(buf, sizeof(buf), "%s/%s/", info->pmu->name, info->name);
err = parse_events(evlist, buf, &parse_err);
if (err) {
parse_events_error__print(&parse_err, buf);
*ret = TEST_FAIL;
}
parse_events_error__exit(&parse_err);
evlist__for_each_entry(evlist, evsel) {
bool fail = false;
bool p_core_pmu = evsel->pmu->type == PERF_TYPE_RAW;
const char *name = evsel__name(evsel);
if (strcasestr(name, "uops_retired.slots") ||
strcasestr(name, "topdown.backend_bound_slots") ||
strcasestr(name, "topdown.br_mispredict_slots") ||
strcasestr(name, "topdown.memory_bound_slots") ||
strcasestr(name, "topdown.bad_spec_slots") ||
strcasestr(name, "topdown.slots_p")) {
if (arch_is_topdown_slots(evsel) || arch_is_topdown_metrics(evsel))
fail = true;
} else if (strcasestr(name, "slots")) {
if (arch_is_topdown_slots(evsel) != p_core_pmu ||
arch_is_topdown_metrics(evsel))
fail = true;
} else if (strcasestr(name, "topdown")) {
if (arch_is_topdown_slots(evsel) ||
arch_is_topdown_metrics(evsel) != p_core_pmu)
fail = true;
} else if (arch_is_topdown_slots(evsel) || arch_is_topdown_metrics(evsel)) {
fail = true;
}
if (fail) {
pr_debug("Broken topdown information for '%s'\n", evsel__name(evsel));
*ret = TEST_FAIL;
}
}
evlist__delete(evlist);
return 0;
}
static int test__x86_topdown(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
int ret = TEST_OK;
struct perf_pmu *pmu = NULL;
if (!topdown_sys_has_perf_metrics())
return TEST_OK;
while ((pmu = perf_pmus__scan_core(pmu)) != NULL) {
if (perf_pmu__for_each_event(pmu, /*skip_duplicate_pmus=*/false, &ret, event_cb))
break;
}
return ret;
}
DEFINE_SUITE("x86 topdown", x86_topdown);

46
tools/perf/arch/x86/util/event.c
View File

@@ -91,49 +91,3 @@ int perf_event__synthesize_extra_kmaps(const struct perf_tool *tool,
}
#endif
void arch_perf_parse_sample_weight(struct perf_sample *data,
const __u64 *array, u64 type)
{
union perf_sample_weight weight;
weight.full = *array;
if (type & PERF_SAMPLE_WEIGHT)
data->weight = weight.full;
else {
data->weight = weight.var1_dw;
data->ins_lat = weight.var2_w;
data->retire_lat = weight.var3_w;
}
}
void arch_perf_synthesize_sample_weight(const struct perf_sample *data,
__u64 *array, u64 type)
{
*array = data->weight;
if (type & PERF_SAMPLE_WEIGHT_STRUCT) {
*array &= 0xffffffff;
*array |= ((u64)data->ins_lat << 32);
*array |= ((u64)data->retire_lat << 48);
}
}
const char *arch_perf_header_entry(const char *se_header)
{
if (!strcmp(se_header, "Local Pipeline Stage Cycle"))
return "Local Retire Latency";
else if (!strcmp(se_header, "Pipeline Stage Cycle"))
return "Retire Latency";
return se_header;
}
int arch_support_sort_key(const char *sort_key)
{
if (!strcmp(sort_key, "p_stage_cyc"))
return 1;
if (!strcmp(sort_key, "local_p_stage_cyc"))
return 1;
return 0;
}

24
tools/perf/arch/x86/util/evlist.c
View File

@@ -81,3 +81,27 @@ int arch_evlist__cmp(const struct evsel *lhs, const struct evsel *rhs)
/* Default ordering by insertion index. */
return lhs->core.idx - rhs->core.idx;
}
int arch_evlist__add_required_events(struct list_head *list)
{
struct evsel *pos, *metric_event = NULL;
int idx = 0;
if (!topdown_sys_has_perf_metrics())
return 0;
list_for_each_entry(pos, list, core.node) {
if (arch_is_topdown_slots(pos)) {
/* Slots event already present, nothing to do. */
return 0;
}
if (metric_event == NULL && arch_is_topdown_metrics(pos))
metric_event = pos;
idx++;
}
if (metric_event == NULL) {
/* No topdown metric events, nothing to do. */
return 0;
}
return topdown_insert_slots_event(list, idx + 1, metric_event);
}

46
tools/perf/arch/x86/util/evsel.c
View File

@@ -23,47 +23,25 @@ void arch_evsel__set_sample_weight(struct evsel *evsel)
bool evsel__sys_has_perf_metrics(const struct evsel *evsel)
{
struct perf_pmu *pmu;
u32 type = evsel->core.attr.type;
if (!topdown_sys_has_perf_metrics())
return false;
/*
* The PERF_TYPE_RAW type is the core PMU type, e.g., "cpu" PMU
* on a non-hybrid machine, "cpu_core" PMU on a hybrid machine.
* The slots event is only available for the core PMU, which
* supports the perf metrics feature.
* Checking both the PERF_TYPE_RAW type and the slots event
* should be good enough to detect the perf metrics feature.
* The PERF_TYPE_RAW type is the core PMU type, e.g., "cpu" PMU on a
* non-hybrid machine, "cpu_core" PMU on a hybrid machine. The
* topdown_sys_has_perf_metrics checks the slots event is only available
* for the core PMU, which supports the perf metrics feature. Checking
* both the PERF_TYPE_RAW type and the slots event should be good enough
* to detect the perf metrics feature.
*/
again:
switch (type) {
case PERF_TYPE_HARDWARE:
case PERF_TYPE_HW_CACHE:
type = evsel->core.attr.config >> PERF_PMU_TYPE_SHIFT;
if (type)
goto again;
break;
case PERF_TYPE_RAW:
break;
default:
return false;
}
pmu = evsel->pmu;
if (pmu && perf_pmu__is_fake(pmu))
pmu = NULL;
if (!pmu) {
while ((pmu = perf_pmus__scan_core(pmu)) != NULL) {
if (pmu->type == PERF_TYPE_RAW)
break;
}
}
return pmu && perf_pmu__have_event(pmu, "slots");
pmu = evsel__find_pmu(evsel);
return pmu && pmu->type == PERF_TYPE_RAW;
}
bool arch_evsel__must_be_in_group(const struct evsel *evsel)
{
if (!evsel__sys_has_perf_metrics(evsel) || !evsel->name ||
strcasestr(evsel->name, "uops_retired.slots"))
if (!evsel__sys_has_perf_metrics(evsel))
return false;
return arch_is_topdown_metrics(evsel) || arch_is_topdown_slots(evsel);

59
tools/perf/arch/x86/util/topdown.c
View File

@@ -1,6 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
#include "api/fs/fs.h"
#include "util/evsel.h"
#include "util/evlist.h"
#include "util/pmu.h"
#include "util/pmus.h"
@@ -8,6 +6,9 @@
#include "topdown.h"
#include "evsel.h"
// cmask=0, inv=0, pc=0, edge=0, umask=4, event=0
#define TOPDOWN_SLOTS 0x0400
/* Check whether there is a PMU which supports the perf metrics. */
bool topdown_sys_has_perf_metrics(void)
{
@@ -32,31 +33,19 @@ bool topdown_sys_has_perf_metrics(void)
return has_perf_metrics;
}
#define TOPDOWN_SLOTS 0x0400
bool arch_is_topdown_slots(const struct evsel *evsel)
{
if (evsel->core.attr.config == TOPDOWN_SLOTS)
return true;
return false;
return evsel->core.attr.type == PERF_TYPE_RAW &&
evsel->core.attr.config == TOPDOWN_SLOTS &&
evsel->core.attr.config1 == 0;
}
bool arch_is_topdown_metrics(const struct evsel *evsel)
{
int config = evsel->core.attr.config;
const char *name_from_config;
struct perf_pmu *pmu;
/* All topdown events have an event code of 0. */
if ((config & 0xFF) != 0)
return false;
pmu = evsel__find_pmu(evsel);
if (!pmu || !pmu->is_core)
return false;
name_from_config = perf_pmu__name_from_config(pmu, config);
return name_from_config && strcasestr(name_from_config, "topdown");
// cmask=0, inv=0, pc=0, edge=0, umask=0x80-0x87, event=0
return evsel->core.attr.type == PERF_TYPE_RAW &&
(evsel->core.attr.config & 0xFFFFF8FF) == 0x8000 &&
evsel->core.attr.config1 == 0;
}
/*
@@ -88,3 +77,31 @@ bool arch_topdown_sample_read(struct evsel *leader)
return false;
}
/*
* Make a copy of the topdown metric event metric_event with the given index but
* change its configuration to be a topdown slots event. Copying from
* metric_event ensures modifiers are the same.
*/
int topdown_insert_slots_event(struct list_head *list, int idx, struct evsel *metric_event)
{
struct evsel *evsel = evsel__new_idx(&metric_event->core.attr, idx);
if (!evsel)
return -ENOMEM;
evsel->core.attr.config = TOPDOWN_SLOTS;
evsel->core.cpus = perf_cpu_map__get(metric_event->core.cpus);
evsel->core.pmu_cpus = perf_cpu_map__get(metric_event->core.pmu_cpus);
evsel->core.is_pmu_core = true;
evsel->pmu = metric_event->pmu;
evsel->name = strdup("slots");
evsel->precise_max = metric_event->precise_max;
evsel->sample_read = metric_event->sample_read;
evsel->weak_group = metric_event->weak_group;
evsel->bpf_counter = metric_event->bpf_counter;
evsel->retire_lat = metric_event->retire_lat;
evsel__set_leader(evsel, evsel__leader(metric_event));
list_add_tail(&evsel->core.node, list);
return 0;
}

6
tools/perf/arch/x86/util/topdown.h
View File

@@ -2,8 +2,14 @@
#ifndef _TOPDOWN_H
#define _TOPDOWN_H 1
#include <stdbool.h>
struct evsel;
struct list_head;
bool topdown_sys_has_perf_metrics(void);
bool arch_is_topdown_slots(const struct evsel *evsel);
bool arch_is_topdown_metrics(const struct evsel *evsel);
int topdown_insert_slots_event(struct list_head *list, int idx, struct evsel *metric_event);
#endif

36
tools/perf/bench/evlist-open-close.c
View File

@@ -57,7 +57,7 @@ static int evlist__count_evsel_fds(struct evlist *evlist)
return cnt;
}
static struct evlist *bench__create_evlist(char *evstr)
static struct evlist *bench__create_evlist(char *evstr, const char *uid_str)
{
struct parse_events_error err;
struct evlist *evlist = evlist__new();
@@ -78,6 +78,18 @@ static struct evlist *bench__create_evlist(char *evstr)
goto out_delete_evlist;
}
parse_events_error__exit(&err);
if (uid_str) {
uid_t uid = parse_uid(uid_str);
if (uid == UINT_MAX) {
pr_err("Invalid User: %s", uid_str);
ret = -EINVAL;
goto out_delete_evlist;
}
ret = parse_uid_filter(evlist, uid);
if (ret)
goto out_delete_evlist;
}
ret = evlist__create_maps(evlist, &opts.target);
if (ret < 0) {
pr_err("Not enough memory to create thread/cpu maps\n");
@@ -117,10 +129,10 @@ static int bench__do_evlist_open_close(struct evlist *evlist)
return 0;
}
static int bench_evlist_open_close__run(char *evstr)
static int bench_evlist_open_close__run(char *evstr, const char *uid_str)
{
// used to print statistics only
struct evlist *evlist = bench__create_evlist(evstr);
struct evlist *evlist = bench__create_evlist(evstr, uid_str);
double time_average, time_stddev;
struct timeval start, end, diff;
struct stats time_stats;
@@ -142,7 +154,7 @@ static int bench_evlist_open_close__run(char *evstr)
for (i = 0; i < iterations; i++) {
pr_debug("Started iteration %d\n", i);
evlist = bench__create_evlist(evstr);
evlist = bench__create_evlist(evstr, uid_str);
if (!evlist)
return -ENOMEM;
@@ -206,6 +218,7 @@ static char *bench__repeat_event_string(const char *evstr, int n)
int bench_evlist_open_close(int argc, const char **argv)
{
const char *uid_str = NULL;
const struct option options[] = {
OPT_STRING('e', "event", &event_string, "event",
"event selector. use 'perf list' to list available events"),
@@ -221,7 +234,7 @@ int bench_evlist_open_close(int argc, const char **argv)
"record events on existing process id"),
OPT_STRING('t', "tid", &opts.target.tid, "tid",
"record events on existing thread id"),
OPT_STRING('u', "uid", &opts.target.uid_str, "user", "user to profile"),
OPT_STRING('u', "uid", &uid_str, "user", "user to profile"),
OPT_BOOLEAN(0, "per-thread", &opts.target.per_thread, "use per-thread mmaps"),
OPT_END()
};
@@ -245,15 +258,8 @@ int bench_evlist_open_close(int argc, const char **argv)
goto out;
}
err = target__parse_uid(&opts.target);
if (err) {
target__strerror(&opts.target, err, errbuf, sizeof(errbuf));
pr_err("%s", errbuf);
goto out;
}
/* Enable ignoring missing threads when -u/-p option is defined. */
opts.ignore_missing_thread = opts.target.uid != UINT_MAX || opts.target.pid;
/* Enable ignoring missing threads when -p option is defined. */
opts.ignore_missing_thread = opts.target.pid;
evstr = bench__repeat_event_string(event_string, nr_events);
if (!evstr) {
@@ -261,7 +267,7 @@ int bench_evlist_open_close(int argc, const char **argv)
goto out;
}
err = bench_evlist_open_close__run(evstr);
err = bench_evlist_open_close__run(evstr, uid_str);
free(evstr);
out:

2
tools/perf/bench/inject-buildid.c
View File

@@ -80,7 +80,7 @@ static int add_dso(const char *fpath, const struct stat *sb __maybe_unused,
int typeflag, struct FTW *ftwbuf __maybe_unused)
{
struct bench_dso *dso = &dsos[nr_dsos];
struct build_id bid;
struct build_id bid = { .size = 0, };
if (typeflag == FTW_D || typeflag == FTW_SL)
return 0;

27
tools/perf/bench/synthesize.c
View File

@@ -114,12 +114,16 @@ static int run_single_threaded(void)
.pid = "self",
};
struct perf_thread_map *threads;
struct perf_env host_env;
int err;
perf_set_singlethreaded();
session = perf_session__new(NULL, NULL);
perf_env__init(&host_env);
session = __perf_session__new(/*data=*/NULL, /*tool=*/NULL,
/*trace_event_repipe=*/false, &host_env);
if (IS_ERR(session)) {
pr_err("Session creation failed.\n");
perf_env__exit(&host_env);
return PTR_ERR(session);
}
threads = thread_map__new_by_pid(getpid());
@@ -144,6 +148,7 @@ static int run_single_threaded(void)
perf_thread_map__put(threads);
perf_session__delete(session);
perf_env__exit(&host_env);
return err;
}
@@ -154,17 +159,21 @@ static int do_run_multi_threaded(struct target *target,
u64 runtime_us;
unsigned int i;
double time_average, time_stddev, event_average, event_stddev;
int err;
int err = 0;
struct stats time_stats, event_stats;
struct perf_session *session;
struct perf_env host_env;
perf_env__init(&host_env);
init_stats(&time_stats);
init_stats(&event_stats);
for (i = 0; i < multi_iterations; i++) {
session = perf_session__new(NULL, NULL);
if (IS_ERR(session))
return PTR_ERR(session);
session = __perf_session__new(/*data=*/NULL, /*tool=*/NULL,
/*trace_event_repipe=*/false, &host_env);
if (IS_ERR(session)) {
err = PTR_ERR(session);
goto err_out;
}
atomic_set(&event_count, 0);
gettimeofday(&start, NULL);
err = __machine__synthesize_threads(&session->machines.host,
@@ -175,7 +184,7 @@ static int do_run_multi_threaded(struct target *target,
nr_threads_synthesize);
if (err) {
perf_session__delete(session);
return err;
goto err_out;
}
gettimeofday(&end, NULL);
@@ -198,7 +207,9 @@ static int do_run_multi_threaded(struct target *target,
printf(" Average time per event %.3f usec\n",
time_average / event_average);
return 0;
err_out:
perf_env__exit(&host_env);
return err;
}
static int run_multi_threaded(void)

6
tools/perf/builtin-annotate.c
View File

@@ -562,7 +562,7 @@ static int __cmd_annotate(struct perf_annotate *ann)
}
if (!annotate_opts.objdump_path) {
ret = perf_env__lookup_objdump(&session->header.env,
ret = perf_env__lookup_objdump(perf_session__env(session),
&annotate_opts.objdump_path);
if (ret)
goto out;
@@ -896,7 +896,7 @@ int cmd_annotate(int argc, const char **argv)
symbol_conf.try_vmlinux_path = true;
ret = symbol__init(&annotate.session->header.env);
ret = symbol__init(perf_session__env(annotate.session));
if (ret < 0)
goto out_delete;
@@ -947,7 +947,7 @@ int cmd_annotate(int argc, const char **argv)
annotate_opts.show_br_cntr = true;
}
if (setup_sorting(NULL) < 0)
if (setup_sorting(/*evlist=*/NULL, perf_session__env(annotate.session)) < 0)
usage_with_options(annotate_usage, options);
ret = __cmd_annotate(&annotate);

22
tools/perf/builtin-buildid-cache.c
View File

@@ -31,7 +31,7 @@
#include <linux/string.h>
#include <linux/err.h>
static int build_id_cache__kcore_buildid(const char *proc_dir, char *sbuildid)
static int build_id_cache__kcore_buildid(const char *proc_dir, char *sbuildid, size_t sbuildid_size)
{
char root_dir[PATH_MAX];
char *p;
@@ -42,7 +42,7 @@ static int build_id_cache__kcore_buildid(const char *proc_dir, char *sbuildid)
if (!p)
return -1;
*p = '\0';
return sysfs__sprintf_build_id(root_dir, sbuildid);
return sysfs__snprintf_build_id(root_dir, sbuildid, sbuildid_size);
}
static int build_id_cache__kcore_dir(char *dir, size_t sz)
@@ -128,7 +128,7 @@ static int build_id_cache__add_kcore(const char *filename, bool force)
return -1;
*p = '\0';
if (build_id_cache__kcore_buildid(from_dir, sbuildid) < 0)
if (build_id_cache__kcore_buildid(from_dir, sbuildid, sizeof(sbuildid)) < 0)
return -1;
scnprintf(to_dir, sizeof(to_dir), "%s/%s/%s",
@@ -175,7 +175,7 @@ static int build_id_cache__add_kcore(const char *filename, bool force)
static int build_id_cache__add_file(const char *filename, struct nsinfo *nsi)
{
char sbuild_id[SBUILD_ID_SIZE];
struct build_id bid;
struct build_id bid = { .size = 0, };
int err;
struct nscookie nsc;
@@ -187,7 +187,7 @@ static int build_id_cache__add_file(const char *filename, struct nsinfo *nsi)
return -1;
}
build_id__sprintf(&bid, sbuild_id);
build_id__snprintf(&bid, sbuild_id, sizeof(sbuild_id));
err = build_id_cache__add_s(sbuild_id, filename, nsi,
false, false);
pr_debug("Adding %s %s: %s\n", sbuild_id, filename,
@@ -198,7 +198,7 @@ static int build_id_cache__add_file(const char *filename, struct nsinfo *nsi)
static int build_id_cache__remove_file(const char *filename, struct nsinfo *nsi)
{
char sbuild_id[SBUILD_ID_SIZE];
struct build_id bid;
struct build_id bid = { .size = 0, };
struct nscookie nsc;
int err;
@@ -211,7 +211,7 @@ static int build_id_cache__remove_file(const char *filename, struct nsinfo *nsi)
return -1;
}
build_id__sprintf(&bid, sbuild_id);
build_id__snprintf(&bid, sbuild_id, sizeof(sbuild_id));
err = build_id_cache__remove_s(sbuild_id);
pr_debug("Removing %s %s: %s\n", sbuild_id, filename,
err ? "FAIL" : "Ok");
@@ -275,7 +275,7 @@ static int build_id_cache__purge_all(void)
static bool dso__missing_buildid_cache(struct dso *dso, int parm __maybe_unused)
{
char filename[PATH_MAX];
struct build_id bid;
struct build_id bid = { .size = 0, };
if (!dso__build_id_filename(dso, filename, sizeof(filename), false))
return true;
@@ -303,7 +303,7 @@ static int build_id_cache__fprintf_missing(struct perf_session *session, FILE *f
static int build_id_cache__update_file(const char *filename, struct nsinfo *nsi)
{
char sbuild_id[SBUILD_ID_SIZE];
struct build_id bid;
struct build_id bid = { .size = 0, };
struct nscookie nsc;
int err;
@@ -317,7 +317,7 @@ static int build_id_cache__update_file(const char *filename, struct nsinfo *nsi)
}
err = 0;
build_id__sprintf(&bid, sbuild_id);
build_id__snprintf(&bid, sbuild_id, sizeof(sbuild_id));
if (build_id_cache__cached(sbuild_id))
err = build_id_cache__remove_s(sbuild_id);
@@ -453,7 +453,7 @@ int cmd_buildid_cache(int argc, const char **argv)
return PTR_ERR(session);
}
if (symbol__init(session ? &session->header.env : NULL) < 0)
if (symbol__init(session ? perf_session__env(session) : NULL) < 0)
goto out;
setup_pager();

11
tools/perf/builtin-buildid-list.c
View File

@@ -31,7 +31,7 @@ static int buildid__map_cb(struct map *map, void *arg __maybe_unused)
memset(bid_buf, 0, sizeof(bid_buf));
if (dso__has_build_id(dso))
build_id__sprintf(dso__bid_const(dso), bid_buf);
build_id__snprintf(dso__bid(dso), bid_buf, sizeof(bid_buf));
printf("%s %16" PRIx64 " %16" PRIx64, bid_buf, map__start(map), map__end(map));
if (dso_long_name != NULL)
printf(" %s", dso_long_name);
@@ -45,11 +45,14 @@ static int buildid__map_cb(struct map *map, void *arg __maybe_unused)
static void buildid__show_kernel_maps(void)
{
struct perf_env host_env;
struct machine *machine;
machine = machine__new_host();
perf_env__init(&host_env);
machine = machine__new_host(&host_env);
machine__for_each_kernel_map(machine, buildid__map_cb, NULL);
machine__delete(machine);
perf_env__exit(&host_env);
}
static int sysfs__fprintf_build_id(FILE *fp)
@@ -57,7 +60,7 @@ static int sysfs__fprintf_build_id(FILE *fp)
char sbuild_id[SBUILD_ID_SIZE];
int ret;
ret = sysfs__sprintf_build_id("/", sbuild_id);
ret = sysfs__snprintf_build_id("/", sbuild_id, sizeof(sbuild_id));
if (ret != sizeof(sbuild_id))
return ret < 0 ? ret : -EINVAL;
@@ -69,7 +72,7 @@ static int filename__fprintf_build_id(const char *name, FILE *fp)
char sbuild_id[SBUILD_ID_SIZE];
int ret;
ret = filename__sprintf_build_id(name, sbuild_id);
ret = filename__snprintf_build_id(name, sbuild_id, sizeof(sbuild_id));
if (ret != sizeof(sbuild_id))
return ret < 0 ? ret : -EINVAL;

69
tools/perf/builtin-c2c.c
View File

@@ -195,12 +195,14 @@ static struct hist_entry_ops c2c_entry_ops = {
static int c2c_hists__init(struct c2c_hists *hists,
const char *sort,
int nr_header_lines);
int nr_header_lines,
struct perf_env *env);
static struct c2c_hists*
he__get_c2c_hists(struct hist_entry *he,
const char *sort,
int nr_header_lines)
int nr_header_lines,
struct perf_env *env)
{
struct c2c_hist_entry *c2c_he;
struct c2c_hists *hists;
@@ -214,7 +216,7 @@ he__get_c2c_hists(struct hist_entry *he,
if (!hists)
return NULL;
ret = c2c_hists__init(hists, sort, nr_header_lines);
ret = c2c_hists__init(hists, sort, nr_header_lines, env);
if (ret) {
free(hists);
return NULL;
@@ -350,7 +352,7 @@ static int process_sample_event(const struct perf_tool *tool __maybe_unused,
mi = mi_dup;
c2c_hists = he__get_c2c_hists(he, c2c.cl_sort, 2);
c2c_hists = he__get_c2c_hists(he, c2c.cl_sort, 2, machine->env);
if (!c2c_hists)
goto free_mi;
@@ -1966,7 +1968,8 @@ static struct c2c_fmt *get_format(const char *name)
return c2c_fmt;
}
static int c2c_hists__init_output(struct perf_hpp_list *hpp_list, char *name)
static int c2c_hists__init_output(struct perf_hpp_list *hpp_list, char *name,
struct perf_env *env __maybe_unused)
{
struct c2c_fmt *c2c_fmt = get_format(name);
int level = 0;
@@ -1980,14 +1983,14 @@ static int c2c_hists__init_output(struct perf_hpp_list *hpp_list, char *name)
return 0;
}
static int c2c_hists__init_sort(struct perf_hpp_list *hpp_list, char *name)
static int c2c_hists__init_sort(struct perf_hpp_list *hpp_list, char *name, struct perf_env *env)
{
struct c2c_fmt *c2c_fmt = get_format(name);
struct c2c_dimension *dim;
if (!c2c_fmt) {
reset_dimensions();
return sort_dimension__add(hpp_list, name, NULL, 0);
return sort_dimension__add(hpp_list, name, /*evlist=*/NULL, env, /*level=*/0);
}
dim = c2c_fmt->dim;
@@ -2008,7 +2011,7 @@ static int c2c_hists__init_sort(struct perf_hpp_list *hpp_list, char *name)
\
for (tok = strtok_r((char *)_list, ", ", &tmp); \
tok; tok = strtok_r(NULL, ", ", &tmp)) { \
ret = _fn(hpp_list, tok); \
ret = _fn(hpp_list, tok, env); \
if (ret == -EINVAL) { \
pr_err("Invalid --fields key: `%s'", tok); \
break; \
@@ -2021,7 +2024,8 @@ static int c2c_hists__init_sort(struct perf_hpp_list *hpp_list, char *name)
static int hpp_list__parse(struct perf_hpp_list *hpp_list,
const char *output_,
const char *sort_)
const char *sort_,
struct perf_env *env)
{
char *output = output_ ? strdup(output_) : NULL;
char *sort = sort_ ? strdup(sort_) : NULL;
@@ -2052,7 +2056,8 @@ static int hpp_list__parse(struct perf_hpp_list *hpp_list,
static int c2c_hists__init(struct c2c_hists *hists,
const char *sort,
int nr_header_lines)
int nr_header_lines,
struct perf_env *env)
{
__hists__init(&hists->hists, &hists->list);
@@ -2066,15 +2071,16 @@ static int c2c_hists__init(struct c2c_hists *hists,
/* Overload number of header lines.*/
hists->list.nr_header_lines = nr_header_lines;
return hpp_list__parse(&hists->list, NULL, sort);
return hpp_list__parse(&hists->list, /*output=*/NULL, sort, env);
}
static int c2c_hists__reinit(struct c2c_hists *c2c_hists,
const char *output,
const char *sort)
const char *sort,
struct perf_env *env)
{
perf_hpp__reset_output_field(&c2c_hists->list);
return hpp_list__parse(&c2c_hists->list, output, sort);
return hpp_list__parse(&c2c_hists->list, output, sort, env);
}
#define DISPLAY_LINE_LIMIT 0.001
@@ -2207,8 +2213,9 @@ static int filter_cb(struct hist_entry *he, void *arg __maybe_unused)
return 0;
}
static int resort_cl_cb(struct hist_entry *he, void *arg __maybe_unused)
static int resort_cl_cb(struct hist_entry *he, void *arg)
{
struct perf_env *env = arg;
struct c2c_hist_entry *c2c_he;
struct c2c_hists *c2c_hists;
bool display = he__display(he, &c2c.shared_clines_stats);
@@ -2222,7 +2229,7 @@ static int resort_cl_cb(struct hist_entry *he, void *arg __maybe_unused)
c2c_he->cacheline_idx = idx++;
calc_width(c2c_he);
c2c_hists__reinit(c2c_hists, c2c.cl_output, c2c.cl_resort);
c2c_hists__reinit(c2c_hists, c2c.cl_output, c2c.cl_resort, env);
hists__collapse_resort(&c2c_hists->hists, NULL);
hists__output_resort_cb(&c2c_hists->hists, NULL, filter_cb);
@@ -2267,14 +2274,15 @@ static int setup_nodes(struct perf_session *session)
int node, idx;
struct perf_cpu cpu;
int *cpu2node;
struct perf_env *env = perf_session__env(session);
if (c2c.node_info > 2)
c2c.node_info = 2;
c2c.nodes_cnt = session->header.env.nr_numa_nodes;
c2c.cpus_cnt = session->header.env.nr_cpus_avail;
c2c.nodes_cnt = env->nr_numa_nodes;
c2c.cpus_cnt = env->nr_cpus_avail;
n = session->header.env.numa_nodes;
n = env->numa_nodes;
if (!n)
return -EINVAL;
@@ -2333,7 +2341,7 @@ static int resort_shared_cl_cb(struct hist_entry *he, void *arg __maybe_unused)
return 0;
}
static int hists__iterate_cb(struct hists *hists, hists__resort_cb_t cb)
static int hists__iterate_cb(struct hists *hists, hists__resort_cb_t cb, void *arg)
{
struct rb_node *next = rb_first_cached(&hists->entries);
int ret = 0;
@@ -2342,7 +2350,7 @@ static int hists__iterate_cb(struct hists *hists, hists__resort_cb_t cb)
struct hist_entry *he;
he = rb_entry(next, struct hist_entry, rb_node);
ret = cb(he, NULL);
ret = cb(he, arg);
if (ret)
break;
next = rb_next(&he->rb_node);
@@ -2448,7 +2456,7 @@ static void print_cacheline(struct c2c_hists *c2c_hists,
hists__fprintf(&c2c_hists->hists, false, 0, 0, 0, out, false);
}
static void print_pareto(FILE *out)
static void print_pareto(FILE *out, struct perf_env *env)
{
struct perf_hpp_list hpp_list;
struct rb_node *nd;
@@ -2473,7 +2481,7 @@ static void print_pareto(FILE *out)
"dcacheline";
perf_hpp_list__init(&hpp_list);
ret = hpp_list__parse(&hpp_list, cl_output, NULL);
ret = hpp_list__parse(&hpp_list, cl_output, /*evlist=*/NULL, env);
if (WARN_ONCE(ret, "failed to setup sort entries\n"))
return;
@@ -2538,7 +2546,7 @@ static void perf_c2c__hists_fprintf(FILE *out, struct perf_session *session)
fprintf(out, "=================================================\n");
fprintf(out, "#\n");
print_pareto(out);
print_pareto(out, perf_session__env(session));
}
#ifdef HAVE_SLANG_SUPPORT
@@ -3030,6 +3038,7 @@ static int perf_c2c__report(int argc, const char **argv)
};
int err = 0;
const char *output_str, *sort_str = NULL;
struct perf_env *env;
argc = parse_options(argc, argv, options, report_c2c_usage,
PARSE_OPT_STOP_AT_NON_OPTION);
@@ -3072,14 +3081,14 @@ static int perf_c2c__report(int argc, const char **argv)
pr_debug("Error creating perf session\n");
goto out;
}
env = perf_session__env(session);
/*
* Use the 'tot' as default display type if user doesn't specify it;
* since Arm64 platform doesn't support HITMs flag, use 'peer' as the
* default display type.
*/
if (!display) {
if (!strcmp(perf_env__arch(&session->header.env), "arm64"))
if (!strcmp(perf_env__arch(env), "arm64"))
display = "peer";
else
display = "tot";
@@ -3095,7 +3104,7 @@ static int perf_c2c__report(int argc, const char **argv)
goto out_session;
}
err = c2c_hists__init(&c2c.hists, "dcacheline", 2);
err = c2c_hists__init(&c2c.hists, "dcacheline", 2, perf_session__env(session));
if (err) {
pr_debug("Failed to initialize hists\n");
goto out_session;
@@ -3109,7 +3118,7 @@ static int perf_c2c__report(int argc, const char **argv)
goto out_session;
}
err = mem2node__init(&c2c.mem2node, &session->header.env);
err = mem2node__init(&c2c.mem2node, env);
if (err)
goto out_session;
@@ -3117,7 +3126,7 @@ static int perf_c2c__report(int argc, const char **argv)
if (err)
goto out_mem2node;
if (symbol__init(&session->header.env) < 0)
if (symbol__init(env) < 0)
goto out_mem2node;
/* No pipe support at the moment. */
@@ -3179,13 +3188,13 @@ static int perf_c2c__report(int argc, const char **argv)
else if (c2c.display == DISPLAY_SNP_PEER)
sort_str = "tot_peer";
c2c_hists__reinit(&c2c.hists, output_str, sort_str);
c2c_hists__reinit(&c2c.hists, output_str, sort_str, perf_session__env(session));
ui_progress__init(&prog, c2c.hists.hists.nr_entries, "Sorting...");
hists__collapse_resort(&c2c.hists.hists, NULL);
hists__output_resort_cb(&c2c.hists.hists, &prog, resort_shared_cl_cb);
hists__iterate_cb(&c2c.hists.hists, resort_cl_cb);
hists__iterate_cb(&c2c.hists.hists, resort_cl_cb, perf_session__env(session));
ui_progress__finish();

2
tools/perf/builtin-check.c
View File

@@ -43,8 +43,8 @@ struct feature_status supported_features[] = {
FEATURE_STATUS("dwarf-unwind", HAVE_DWARF_UNWIND_SUPPORT),
FEATURE_STATUS("auxtrace", HAVE_AUXTRACE_SUPPORT),
FEATURE_STATUS_TIP("libbfd", HAVE_LIBBFD_SUPPORT, "Deprecated, license incompatibility, use BUILD_NONDISTRO=1 and install binutils-dev[el]"),
FEATURE_STATUS("libbpf-strings", HAVE_LIBBPF_STRINGS_SUPPORT),
FEATURE_STATUS("libcapstone", HAVE_LIBCAPSTONE_SUPPORT),
FEATURE_STATUS("libcrypto", HAVE_LIBCRYPTO_SUPPORT),
FEATURE_STATUS("libdw-dwarf-unwind", HAVE_LIBDW_SUPPORT),
FEATURE_STATUS("libelf", HAVE_LIBELF_SUPPORT),
FEATURE_STATUS("libnuma", HAVE_LIBNUMA_SUPPORT),

2
tools/perf/builtin-diff.c
View File

@@ -2003,7 +2003,7 @@ int cmd_diff(int argc, const char **argv)
sort__mode = SORT_MODE__DIFF;
}
if (setup_sorting(NULL) < 0)
if (setup_sorting(/*evlist=*/NULL, perf_session__env(data__files[0].session)) < 0)
usage_with_options(diff_usage, options);
setup_pager();

111
tools/perf/builtin-ftrace.c
View File

@@ -301,6 +301,10 @@ static void reset_tracing_options(struct perf_ftrace *ftrace __maybe_unused)
write_tracing_option_file("funcgraph-proc", "0");
write_tracing_option_file("funcgraph-abstime", "0");
write_tracing_option_file("funcgraph-tail", "0");
write_tracing_option_file("funcgraph-args", "0");
write_tracing_option_file("funcgraph-retval", "0");
write_tracing_option_file("funcgraph-retval-hex", "0");
write_tracing_option_file("funcgraph-retaddr", "0");
write_tracing_option_file("latency-format", "0");
write_tracing_option_file("irq-info", "0");
}
@@ -542,6 +546,41 @@ static int set_tracing_sleep_time(struct perf_ftrace *ftrace)
return 0;
}
static int set_tracing_funcgraph_args(struct perf_ftrace *ftrace)
{
if (ftrace->graph_args) {
if (write_tracing_option_file("funcgraph-args", "1") < 0)
return -1;
}
return 0;
}
static int set_tracing_funcgraph_retval(struct perf_ftrace *ftrace)
{
if (ftrace->graph_retval || ftrace->graph_retval_hex) {
if (write_tracing_option_file("funcgraph-retval", "1") < 0)
return -1;
}
if (ftrace->graph_retval_hex) {
if (write_tracing_option_file("funcgraph-retval-hex", "1") < 0)
return -1;
}
return 0;
}
static int set_tracing_funcgraph_retaddr(struct perf_ftrace *ftrace)
{
if (ftrace->graph_retaddr) {
if (write_tracing_option_file("funcgraph-retaddr", "1") < 0)
return -1;
}
return 0;
}
static int set_tracing_funcgraph_irqs(struct perf_ftrace *ftrace)
{
if (!ftrace->graph_noirqs)
@@ -642,6 +681,21 @@ static int set_tracing_options(struct perf_ftrace *ftrace)
return -1;
}
if (set_tracing_funcgraph_args(ftrace) < 0) {
pr_err("failed to set tracing option funcgraph-args\n");
return -1;
}
if (set_tracing_funcgraph_retval(ftrace) < 0) {
pr_err("failed to set tracing option funcgraph-retval\n");
return -1;
}
if (set_tracing_funcgraph_retaddr(ftrace) < 0) {
pr_err("failed to set tracing option funcgraph-retaddr\n");
return -1;
}
if (set_tracing_funcgraph_irqs(ftrace) < 0) {
pr_err("failed to set tracing option funcgraph-irqs\n");
return -1;
@@ -1549,6 +1603,33 @@ static void delete_filter_func(struct list_head *head)
}
}
static int parse_filter_event(const struct option *opt, const char *str,
int unset __maybe_unused)
{
struct list_head *head = opt->value;
struct filter_entry *entry;
char *s, *p;
int ret = -ENOMEM;
s = strdup(str);
if (s == NULL)
return -ENOMEM;
while ((p = strsep(&s, ",")) != NULL) {
entry = malloc(sizeof(*entry) + strlen(p) + 1);
if (entry == NULL)
goto out;
strcpy(entry->name, p);
list_add_tail(&entry->list, head);
}
ret = 0;
out:
free(s);
return ret;
}
static int parse_buffer_size(const struct option *opt,
const char *str, int unset)
{
@@ -1607,6 +1688,10 @@ static int parse_graph_tracer_opts(const struct option *opt,
int ret;
struct perf_ftrace *ftrace = (struct perf_ftrace *) opt->value;
struct sublevel_option graph_tracer_opts[] = {
{ .name = "args", .value_ptr = &ftrace->graph_args },
{ .name = "retval", .value_ptr = &ftrace->graph_retval },
{ .name = "retval-hex", .value_ptr = &ftrace->graph_retval_hex },
{ .name = "retaddr", .value_ptr = &ftrace->graph_retaddr },
{ .name = "nosleep-time", .value_ptr = &ftrace->graph_nosleep_time },
{ .name = "noirqs", .value_ptr = &ftrace->graph_noirqs },
{ .name = "verbose", .value_ptr = &ftrace->graph_verbose },
@@ -1663,7 +1748,6 @@ int cmd_ftrace(int argc, const char **argv)
int (*cmd_func)(struct perf_ftrace *) = NULL;
struct perf_ftrace ftrace = {
.tracer = DEFAULT_TRACER,
.target = { .uid = UINT_MAX, },
};
const struct option common_options[] = {
OPT_STRING('p', "pid", &ftrace.target.pid, "pid",
@@ -1699,7 +1783,7 @@ int cmd_ftrace(int argc, const char **argv)
OPT_CALLBACK('g', "nograph-funcs", &ftrace.nograph_funcs, "func",
"Set nograph filter on given functions", parse_filter_func),
OPT_CALLBACK(0, "graph-opts", &ftrace, "options",
"Graph tracer options, available options: nosleep-time,noirqs,verbose,thresh=<n>,depth=<n>",
"Graph tracer options, available options: args,retval,retval-hex,retaddr,nosleep-time,noirqs,verbose,thresh=<n>,depth=<n>",
parse_graph_tracer_opts),
OPT_CALLBACK('m', "buffer-size", &ftrace.percpu_buffer_size, "size",
"Size of per cpu buffer, needs to use a B, K, M or G suffix.", parse_buffer_size),
@@ -1712,6 +1796,8 @@ int cmd_ftrace(int argc, const char **argv)
const struct option latency_options[] = {
OPT_CALLBACK('T', "trace-funcs", &ftrace.filters, "func",
"Show latency of given function", parse_filter_func),
OPT_CALLBACK('e', "events", &ftrace.event_pair, "event1,event2",
"Show latency between the two events", parse_filter_event),
#ifdef HAVE_BPF_SKEL
OPT_BOOLEAN('b', "use-bpf", &ftrace.target.use_bpf,
"Use BPF to measure function latency"),
@@ -1764,6 +1850,7 @@ int cmd_ftrace(int argc, const char **argv)
INIT_LIST_HEAD(&ftrace.notrace);
INIT_LIST_HEAD(&ftrace.graph_funcs);
INIT_LIST_HEAD(&ftrace.nograph_funcs);
INIT_LIST_HEAD(&ftrace.event_pair);
signal(SIGINT, sig_handler);
signal(SIGUSR1, sig_handler);
@@ -1818,9 +1905,24 @@ int cmd_ftrace(int argc, const char **argv)
cmd_func = __cmd_ftrace;
break;
case PERF_FTRACE_LATENCY:
if (list_empty(&ftrace.filters)) {
pr_err("Should provide a function to measure\n");
if (list_empty(&ftrace.filters) && list_empty(&ftrace.event_pair)) {
pr_err("Should provide a function or events to measure\n");
parse_options_usage(ftrace_usage, options, "T", 1);
parse_options_usage(NULL, options, "e", 1);
ret = -EINVAL;
goto out_delete_filters;
}
if (!list_empty(&ftrace.filters) && !list_empty(&ftrace.event_pair)) {
pr_err("Please specify either of function or events\n");
parse_options_usage(ftrace_usage, options, "T", 1);
parse_options_usage(NULL, options, "e", 1);
ret = -EINVAL;
goto out_delete_filters;
}
if (!list_empty(&ftrace.event_pair) && !ftrace.target.use_bpf) {
pr_err("Event processing needs BPF\n");
parse_options_usage(ftrace_usage, options, "b", 1);
parse_options_usage(NULL, options, "e", 1);
ret = -EINVAL;
goto out_delete_filters;
}
@@ -1911,6 +2013,7 @@ int cmd_ftrace(int argc, const char **argv)
delete_filter_func(&ftrace.notrace);
delete_filter_func(&ftrace.graph_funcs);
delete_filter_func(&ftrace.nograph_funcs);
delete_filter_func(&ftrace.event_pair);
return ret;
}

42
tools/perf/builtin-inject.c
View File

@@ -587,15 +587,17 @@ static int perf_event__repipe_mmap2(const struct perf_tool *tool,
struct perf_sample *sample,
struct machine *machine)
{
struct dso_id id;
struct dso_id *dso_id = NULL;
struct dso_id id = dso_id_empty;
if (!(event->header.misc & PERF_RECORD_MISC_MMAP_BUILD_ID)) {
if (event->header.misc & PERF_RECORD_MISC_MMAP_BUILD_ID) {
build_id__init(&id.build_id, event->mmap2.build_id, event->mmap2.build_id_size);
} else {
id.maj = event->mmap2.maj;
id.min = event->mmap2.min;
id.ino = event->mmap2.ino;
id.ino_generation = event->mmap2.ino_generation;
dso_id = &id;
id.mmap2_valid = true;
id.mmap2_ino_generation_valid = true;
}
return perf_event__repipe_common_mmap(
@@ -603,7 +605,7 @@ static int perf_event__repipe_mmap2(const struct perf_tool *tool,
event->mmap2.pid, event->mmap2.tid,
event->mmap2.start, event->mmap2.len, event->mmap2.pgoff,
event->mmap2.flags, event->mmap2.prot,
event->mmap2.filename, dso_id,
event->mmap2.filename, &id,
perf_event__process_mmap2);
}
@@ -671,19 +673,20 @@ static int perf_event__repipe_tracing_data(struct perf_session *session,
static int dso__read_build_id(struct dso *dso)
{
struct nscookie nsc;
struct build_id bid = { .size = 0, };
if (dso__has_build_id(dso))
return 0;
mutex_lock(dso__lock(dso));
nsinfo__mountns_enter(dso__nsinfo(dso), &nsc);
if (filename__read_build_id(dso__long_name(dso), dso__bid(dso)) > 0)
dso__set_has_build_id(dso);
if (filename__read_build_id(dso__long_name(dso), &bid) > 0)
dso__set_build_id(dso, &bid);
else if (dso__nsinfo(dso)) {
char *new_name = dso__filename_with_chroot(dso, dso__long_name(dso));
if (new_name && filename__read_build_id(new_name, dso__bid(dso)) > 0)
dso__set_has_build_id(dso);
if (new_name && filename__read_build_id(new_name, &bid) > 0)
dso__set_build_id(dso, &bid);
free(new_name);
}
nsinfo__mountns_exit(&nsc);
@@ -732,23 +735,26 @@ static bool perf_inject__lookup_known_build_id(struct perf_inject *inject,
struct dso *dso)
{
struct str_node *pos;
int bid_len;
strlist__for_each_entry(pos, inject->known_build_ids) {
struct build_id bid;
const char *build_id, *dso_name;
size_t bid_len;
build_id = skip_spaces(pos->s);
dso_name = strchr(build_id, ' ');
bid_len = dso_name - pos->s;
if (bid_len > sizeof(bid.data))
bid_len = sizeof(bid.data);
dso_name = skip_spaces(dso_name);
if (strcmp(dso__long_name(dso), dso_name))
continue;
for (int ix = 0; 2 * ix + 1 < bid_len; ++ix) {
dso__bid(dso)->data[ix] = (hex(build_id[2 * ix]) << 4 |
hex(build_id[2 * ix + 1]));
for (size_t ix = 0; 2 * ix + 1 < bid_len; ++ix) {
bid.data[ix] = (hex(build_id[2 * ix]) << 4 |
hex(build_id[2 * ix + 1]));
}
dso__bid(dso)->size = bid_len / 2;
dso__set_has_build_id(dso);
bid.size = bid_len / 2;
dso__set_build_id(dso, &bid);
return true;
}
return false;
@@ -2530,9 +2536,11 @@ int cmd_inject(int argc, const char **argv)
inject.tool.finished_init = perf_event__repipe_op2_synth;
inject.tool.compressed = perf_event__repipe_op4_synth;
inject.tool.auxtrace = perf_event__repipe_auxtrace;
inject.tool.bpf_metadata = perf_event__repipe_op2_synth;
inject.tool.dont_split_sample_group = true;
inject.session = __perf_session__new(&data, &inject.tool,
/*trace_event_repipe=*/inject.output.is_pipe);
/*trace_event_repipe=*/inject.output.is_pipe,
/*host_env=*/NULL);
if (IS_ERR(inject.session)) {
ret = PTR_ERR(inject.session);
@@ -2601,7 +2609,7 @@ int cmd_inject(int argc, const char **argv)
inject.tool.finished_round = perf_event__drop_oe;
}
#endif
ret = symbol__init(&inject.session->header.env);
ret = symbol__init(perf_session__env(inject.session));
if (ret < 0)
goto out_delete;

21
tools/perf/builtin-kallsyms.c
View File

@@ -12,18 +12,28 @@
#include <subcmd/parse-options.h>
#include "debug.h"
#include "dso.h"
#include "env.h"
#include "machine.h"
#include "map.h"
#include "symbol.h"
static int __cmd_kallsyms(int argc, const char **argv)
{
int i;
struct machine *machine = machine__new_kallsyms();
int i, err;
struct perf_env host_env;
struct machine *machine = NULL;
perf_env__init(&host_env);
err = perf_env__set_cmdline(&host_env, argc, argv);
if (err)
goto out;
machine = machine__new_kallsyms(&host_env);
if (machine == NULL) {
pr_err("Couldn't read /proc/kallsyms\n");
return -1;
err = -1;
goto out;
}
for (i = 0; i < argc; ++i) {
@@ -42,9 +52,10 @@ static int __cmd_kallsyms(int argc, const char **argv)
map__unmap_ip(map, symbol->start), map__unmap_ip(map, symbol->end),
symbol->start, symbol->end);
}
out:
machine__delete(machine);
return 0;
perf_env__exit(&host_env);
return err;
}
int cmd_kallsyms(int argc, const char **argv)

2
tools/perf/builtin-kmem.c
View File

@@ -2024,7 +2024,7 @@ int cmd_kmem(int argc, const char **argv)
symbol_conf.use_callchain = true;
}
symbol__init(&session->header.env);
symbol__init(perf_session__env(session));
if (perf_time__parse_str(&ptime, time_str) != 0) {
pr_err("Invalid time string\n");

6
tools/perf/builtin-kvm.c
View File

@@ -1175,7 +1175,7 @@ static int cpu_isa_config(struct perf_kvm_stat *kvm)
}
cpuid = buf;
} else
cpuid = kvm->session->header.env.cpuid;
cpuid = perf_session__env(kvm->session)->cpuid;
if (!cpuid) {
pr_err("Failed to look up CPU type\n");
@@ -1561,7 +1561,7 @@ static int read_events(struct perf_kvm_stat *kvm)
return PTR_ERR(kvm->session);
}
symbol__init(&kvm->session->header.env);
symbol__init(perf_session__env(kvm->session));
if (!perf_session__has_traces(kvm->session, "kvm record")) {
ret = -EINVAL;
@@ -1871,8 +1871,6 @@ static int kvm_events_live(struct perf_kvm_stat *kvm,
kvm->opts.user_interval = 1;
kvm->opts.mmap_pages = 512;
kvm->opts.target.uses_mmap = false;
kvm->opts.target.uid_str = NULL;
kvm->opts.target.uid = UINT_MAX;
symbol__init(NULL);
disable_buildid_cache();

2
tools/perf/builtin-kwork.c
View File

@@ -1804,7 +1804,7 @@ static int perf_kwork__read_events(struct perf_kwork *kwork)
return PTR_ERR(session);
}
symbol__init(&session->header.env);
symbol__init(perf_session__env(session));
if (perf_kwork__check_config(kwork, session) != 0)
goto out_delete;

65
tools/perf/builtin-list.c
View File

@@ -58,6 +58,8 @@ struct print_state {
bool metrics;
/** @metricgroups: Controls printing of metric and metric groups. */
bool metricgroups;
/** @exclude_abi: Exclude PMUs with types less than PERF_TYPE_MAX except PERF_TYPE_RAW. */
bool exclude_abi;
/** @last_topic: The last printed event topic. */
char *last_topic;
/** @last_metricgroups: The last printed metric group. */
@@ -113,7 +115,8 @@ static void wordwrap(FILE *fp, const char *s, int start, int max, int corr)
}
}
static void default_print_event(void *ps, const char *topic, const char *pmu_name,
static void default_print_event(void *ps, const char *topic,
const char *pmu_name, u32 pmu_type,
const char *event_name, const char *event_alias,
const char *scale_unit __maybe_unused,
bool deprecated, const char *event_type_desc,
@@ -130,6 +133,9 @@ static void default_print_event(void *ps, const char *topic, const char *pmu_nam
if (print_state->pmu_glob && pmu_name && !strglobmatch(pmu_name, print_state->pmu_glob))
return;
if (print_state->exclude_abi && pmu_type < PERF_TYPE_MAX && pmu_type != PERF_TYPE_RAW)
return;
if (print_state->event_glob &&
(!event_name || !strglobmatch(event_name, print_state->event_glob)) &&
(!event_alias || !strglobmatch(event_alias, print_state->event_glob)) &&
@@ -354,7 +360,8 @@ static void fix_escape_fprintf(FILE *fp, struct strbuf *buf, const char *fmt, ..
fputs(buf->buf, fp);
}
static void json_print_event(void *ps, const char *topic, const char *pmu_name,
static void json_print_event(void *ps, const char *topic,
const char *pmu_name, u32 pmu_type __maybe_unused,
const char *event_name, const char *event_alias,
const char *scale_unit,
bool deprecated, const char *event_type_desc,
@@ -614,19 +621,10 @@ int cmd_list(int argc, const char **argv)
for (i = 0; i < argc; ++i) {
char *sep, *s;
if (strcmp(argv[i], "tracepoint") == 0)
print_tracepoint_events(&print_cb, ps);
else if (strcmp(argv[i], "hw") == 0 ||
strcmp(argv[i], "hardware") == 0)
print_symbol_events(&print_cb, ps, PERF_TYPE_HARDWARE,
event_symbols_hw, PERF_COUNT_HW_MAX);
else if (strcmp(argv[i], "sw") == 0 ||
strcmp(argv[i], "software") == 0) {
if (strcmp(argv[i], "tracepoint") == 0) {
char *old_pmu_glob = default_ps.pmu_glob;
print_symbol_events(&print_cb, ps, PERF_TYPE_SOFTWARE,
event_symbols_sw, PERF_COUNT_SW_MAX);
default_ps.pmu_glob = strdup("tool");
default_ps.pmu_glob = strdup("tracepoint");
if (!default_ps.pmu_glob) {
ret = -1;
goto out;
@@ -634,12 +632,33 @@ int cmd_list(int argc, const char **argv)
perf_pmus__print_pmu_events(&print_cb, ps);
zfree(&default_ps.pmu_glob);
default_ps.pmu_glob = old_pmu_glob;
} else if (strcmp(argv[i], "hw") == 0 ||
strcmp(argv[i], "hardware") == 0)
print_symbol_events(&print_cb, ps, PERF_TYPE_HARDWARE,
event_symbols_hw, PERF_COUNT_HW_MAX);
else if (strcmp(argv[i], "sw") == 0 ||
strcmp(argv[i], "software") == 0) {
char *old_pmu_glob = default_ps.pmu_glob;
static const char * const sw_globs[] = { "software", "tool" };
for (size_t j = 0; j < ARRAY_SIZE(sw_globs); j++) {
default_ps.pmu_glob = strdup(sw_globs[j]);
if (!default_ps.pmu_glob) {
ret = -1;
goto out;
}
perf_pmus__print_pmu_events(&print_cb, ps);
zfree(&default_ps.pmu_glob);
}
default_ps.pmu_glob = old_pmu_glob;
} else if (strcmp(argv[i], "cache") == 0 ||
strcmp(argv[i], "hwcache") == 0)
print_hwcache_events(&print_cb, ps);
else if (strcmp(argv[i], "pmu") == 0)
else if (strcmp(argv[i], "pmu") == 0) {
default_ps.exclude_abi = true;
perf_pmus__print_pmu_events(&print_cb, ps);
else if (strcmp(argv[i], "sdt") == 0)
default_ps.exclude_abi = false;
} else if (strcmp(argv[i], "sdt") == 0)
print_sdt_events(&print_cb, ps);
else if (strcmp(argv[i], "metric") == 0 || strcmp(argv[i], "metrics") == 0) {
default_ps.metricgroups = false;
@@ -657,6 +676,7 @@ int cmd_list(int argc, const char **argv)
#endif
else if ((sep = strchr(argv[i], ':')) != NULL) {
char *old_pmu_glob = default_ps.pmu_glob;
char *old_event_glob = default_ps.event_glob;
default_ps.event_glob = strdup(argv[i]);
if (!default_ps.event_glob) {
@@ -664,13 +684,21 @@ int cmd_list(int argc, const char **argv)
goto out;
}
print_tracepoint_events(&print_cb, ps);
default_ps.pmu_glob = strdup("tracepoint");
if (!default_ps.pmu_glob) {
zfree(&default_ps.event_glob);
ret = -1;
goto out;
}
perf_pmus__print_pmu_events(&print_cb, ps);
zfree(&default_ps.pmu_glob);
default_ps.pmu_glob = old_pmu_glob;
print_sdt_events(&print_cb, ps);
default_ps.metrics = true;
default_ps.metricgroups = true;
metricgroup__print(&print_cb, ps);
zfree(&default_ps.event_glob);
default_ps.pmu_glob = old_pmu_glob;
default_ps.event_glob = old_event_glob;
} else {
if (asprintf(&s, "*%s*", argv[i]) < 0) {
printf("Critical: Not enough memory! Trying to continue...\n");
@@ -679,11 +707,8 @@ int cmd_list(int argc, const char **argv)
default_ps.event_glob = s;
print_symbol_events(&print_cb, ps, PERF_TYPE_HARDWARE,
event_symbols_hw, PERF_COUNT_HW_MAX);
print_symbol_events(&print_cb, ps, PERF_TYPE_SOFTWARE,
event_symbols_sw, PERF_COUNT_SW_MAX);
print_hwcache_events(&print_cb, ps);
perf_pmus__print_pmu_events(&print_cb, ps);
print_tracepoint_events(&print_cb, ps);
print_sdt_events(&print_cb, ps);
default_ps.metrics = true;
default_ps.metricgroups = true;

4
tools/perf/builtin-lock.c
View File

@@ -1876,7 +1876,7 @@ static int __cmd_report(bool display_info)
}
symbol_conf.allow_aliases = true;
symbol__init(&session->header.env);
symbol__init(perf_session__env(session));
if (!data.is_pipe) {
if (!perf_session__has_traces(session, "lock record"))
@@ -2042,7 +2042,7 @@ static int __cmd_contention(int argc, const char **argv)
con.save_callstack = true;
symbol_conf.allow_aliases = true;
symbol__init(&session->header.env);
symbol__init(perf_session__env(session));
if (use_bpf) {
err = target__validate(&target);

2
tools/perf/builtin-mem.c
View File

@@ -304,7 +304,7 @@ static int report_raw_events(struct perf_mem *mem)
goto out_delete;
}
ret = symbol__init(&session->header.env);
ret = symbol__init(perf_session__env(session));
if (ret < 0)
goto out_delete;

101
tools/perf/builtin-record.c
View File

@@ -171,10 +171,12 @@ struct record {
bool no_buildid_cache_set;
bool buildid_all;
bool buildid_mmap;
bool buildid_mmap_set;
bool timestamp_filename;
bool timestamp_boundary;
bool off_cpu;
const char *filter_action;
const char *uid_str;
struct switch_output switch_output;
unsigned long long samples;
unsigned long output_max_size; /* = 0: unlimited */
@@ -773,7 +775,9 @@ static int record__auxtrace_mmap_read(struct record *rec,
{
int ret;
ret = auxtrace_mmap__read(map, rec->itr, &rec->tool,
ret = auxtrace_mmap__read(map, rec->itr,
perf_session__env(rec->session),
&rec->tool,
record__process_auxtrace);
if (ret < 0)
return ret;
@@ -789,7 +793,9 @@ static int record__auxtrace_mmap_read_snapshot(struct record *rec,
{
int ret;
ret = auxtrace_mmap__read_snapshot(map, rec->itr, &rec->tool,
ret = auxtrace_mmap__read_snapshot(map, rec->itr,
perf_session__env(rec->session),
&rec->tool,
record__process_auxtrace,
rec->opts.auxtrace_snapshot_size);
if (ret < 0)
@@ -1810,6 +1816,7 @@ record__finish_output(struct record *rec)
data->dir.files[i].size = lseek(data->dir.files[i].fd, 0, SEEK_CUR);
}
/* Buildid scanning disabled or build ID in kernel and synthesized map events. */
if (!rec->no_buildid) {
process_buildids(rec);
@@ -2161,6 +2168,14 @@ static int record__synthesize(struct record *rec, bool tail)
return err;
}
static void record__synthesize_final_bpf_metadata(struct record *rec __maybe_unused)
{
#ifdef HAVE_LIBBPF_SUPPORT
perf_event__synthesize_final_bpf_metadata(rec->session,
process_synthesized_event);
#endif
}
static int record__process_signal_event(union perf_event *event __maybe_unused, void *data)
{
struct record *rec = data;
@@ -2192,7 +2207,7 @@ static int record__setup_sb_evlist(struct record *rec)
}
}
if (evlist__add_bpf_sb_event(rec->sb_evlist, &rec->session->header.env)) {
if (evlist__add_bpf_sb_event(rec->sb_evlist, perf_session__env(rec->session))) {
pr_err("Couldn't ask for PERF_RECORD_BPF_EVENT side band events.\n.");
return -1;
}
@@ -2211,15 +2226,16 @@ static int record__init_clock(struct record *rec)
struct perf_session *session = rec->session;
struct timespec ref_clockid;
struct timeval ref_tod;
struct perf_env *env = perf_session__env(session);
u64 ref;
if (!rec->opts.use_clockid)
return 0;
if (rec->opts.use_clockid && rec->opts.clockid_res_ns)
session->header.env.clock.clockid_res_ns = rec->opts.clockid_res_ns;
env->clock.clockid_res_ns = rec->opts.clockid_res_ns;
session->header.env.clock.clockid = rec->opts.clockid;
env->clock.clockid = rec->opts.clockid;
if (gettimeofday(&ref_tod, NULL) != 0) {
pr_err("gettimeofday failed, cannot set reference time.\n");
@@ -2234,12 +2250,12 @@ static int record__init_clock(struct record *rec)
ref = (u64) ref_tod.tv_sec * NSEC_PER_SEC +
(u64) ref_tod.tv_usec * NSEC_PER_USEC;
session->header.env.clock.tod_ns = ref;
env->clock.tod_ns = ref;
ref = (u64) ref_clockid.tv_sec * NSEC_PER_SEC +
(u64) ref_clockid.tv_nsec;
session->header.env.clock.clockid_ns = ref;
env->clock.clockid_ns = ref;
return 0;
}
@@ -2385,6 +2401,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv)
int fd;
float ratio = 0;
enum evlist_ctl_cmd cmd = EVLIST_CTL_CMD_UNSUPPORTED;
struct perf_env *env;
atexit(record__sig_exit);
signal(SIGCHLD, sig_handler);
@@ -2426,7 +2443,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv)
pr_err("Perf session creation failed.\n");
return PTR_ERR(session);
}
env = perf_session__env(session);
if (record__threads_enabled(rec)) {
if (perf_data__is_pipe(&rec->data)) {
pr_err("Parallel trace streaming is not available in pipe mode.\n");
@@ -2460,8 +2477,8 @@ static int __cmd_record(struct record *rec, int argc, const char **argv)
}
#endif // HAVE_EVENTFD_SUPPORT
session->header.env.comp_type = PERF_COMP_ZSTD;
session->header.env.comp_level = rec->opts.comp_level;
env->comp_type = PERF_COMP_ZSTD;
env->comp_level = rec->opts.comp_level;
if (rec->opts.kcore &&
!record__kcore_readable(&session->machines.host)) {
@@ -2514,7 +2531,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv)
}
/* Debug message used by test scripts */
pr_debug3("perf record done opening and mmapping events\n");
session->header.env.comp_mmap_len = session->evlist->core.mmap_len;
env->comp_mmap_len = session->evlist->core.mmap_len;
if (rec->opts.kcore) {
err = record__kcore_copy(&session->machines.host, data);
@@ -2806,6 +2823,8 @@ static int __cmd_record(struct record *rec, int argc, const char **argv)
trigger_off(&auxtrace_snapshot_trigger);
trigger_off(&switch_output_trigger);
record__synthesize_final_bpf_metadata(rec);
if (opts->auxtrace_snapshot_on_exit)
record__auxtrace_snapshot_exit(rec);
@@ -2842,7 +2861,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv)
if (rec->session->bytes_transferred && rec->session->bytes_compressed) {
ratio = (float)rec->session->bytes_transferred/(float)rec->session->bytes_compressed;
session->header.env.comp_ratio = ratio + 0.5;
env->comp_ratio = ratio + 0.5;
}
if (forks) {
@@ -2994,6 +3013,8 @@ static int perf_record_config(const char *var, const char *value, void *cb)
rec->no_buildid = true;
else if (!strcmp(value, "mmap"))
rec->buildid_mmap = true;
else if (!strcmp(value, "no-mmap"))
rec->buildid_mmap = false;
else
return -1;
return 0;
@@ -3400,6 +3421,7 @@ static struct record record = {
.synth = PERF_SYNTH_ALL,
.off_cpu_thresh_ns = OFFCPU_THRESH,
},
.buildid_mmap = true,
};
const char record_callchain_help[] = CALLCHAIN_RECORD_HELP
@@ -3513,8 +3535,7 @@ static struct option __record_options[] = {
"or ranges of time to enable events e.g. '-D 10-20,30-40'",
record__parse_event_enable_time),
OPT_BOOLEAN(0, "kcore", &record.opts.kcore, "copy /proc/kcore"),
OPT_STRING('u', "uid", &record.opts.target.uid_str, "user",
"user to profile"),
OPT_STRING('u', "uid", &record.uid_str, "user", "user to profile"),
OPT_CALLBACK_NOOPT('b', "branch-any", &record.opts.branch_stack,
"branch any", "sample any taken branches",
@@ -3567,8 +3588,8 @@ static struct option __record_options[] = {
"file", "vmlinux pathname"),
OPT_BOOLEAN(0, "buildid-all", &record.buildid_all,
"Record build-id of all DSOs regardless of hits"),
OPT_BOOLEAN(0, "buildid-mmap", &record.buildid_mmap,
"Record build-id in map events"),
OPT_BOOLEAN_SET(0, "buildid-mmap", &record.buildid_mmap, &record.buildid_mmap_set,
"Record build-id in mmap events and skip build-id processing."),
OPT_BOOLEAN(0, "timestamp-filename", &record.timestamp_filename,
"append timestamp to output filename"),
OPT_BOOLEAN(0, "timestamp-boundary", &record.timestamp_boundary,
@@ -4098,19 +4119,24 @@ int cmd_record(int argc, const char **argv)
record.opts.record_switch_events = true;
}
if (!rec->buildid_mmap) {
pr_debug("Disabling build id in synthesized mmap2 events.\n");
symbol_conf.no_buildid_mmap2 = true;
} else if (rec->buildid_mmap_set) {
/*
* Explicitly passing --buildid-mmap disables buildid processing
* and cache generation.
*/
rec->no_buildid = true;
}
if (rec->buildid_mmap && !perf_can_record_build_id()) {
pr_warning("Missing support for build id in kernel mmap events.\n"
"Disable this warning with --no-buildid-mmap\n");
rec->buildid_mmap = false;
}
if (rec->buildid_mmap) {
if (!perf_can_record_build_id()) {
pr_err("Failed: no support to record build id in mmap events, update your kernel.\n");
err = -EINVAL;
goto out_opts;
}
pr_debug("Enabling build id in mmap2 events.\n");
/* Enable mmap build id synthesizing. */
symbol_conf.buildid_mmap2 = true;
/* Enable perf_event_attr::build_id bit. */
rec->opts.build_id = true;
/* Disable build id cache. */
rec->no_buildid = true;
}
if (rec->opts.record_cgroup && !perf_can_record_cgroup()) {
@@ -4256,19 +4282,24 @@ int cmd_record(int argc, const char **argv)
ui__warning("%s\n", errbuf);
}
err = target__parse_uid(&rec->opts.target);
if (err) {
int saved_errno = errno;
if (rec->uid_str) {
uid_t uid = parse_uid(rec->uid_str);
target__strerror(&rec->opts.target, err, errbuf, BUFSIZ);
ui__error("%s", errbuf);
if (uid == UINT_MAX) {
ui__error("Invalid User: %s", rec->uid_str);
err = -EINVAL;
goto out;
}
err = parse_uid_filter(rec->evlist, uid);
if (err)
goto out;
err = -saved_errno;
goto out;
/* User ID filtering implies system wide. */
rec->opts.target.system_wide = true;
}
/* Enable ignoring missing threads when -u/-p option is defined. */
rec->opts.ignore_missing_thread = rec->opts.target.uid != UINT_MAX || rec->opts.target.pid;
/* Enable ignoring missing threads when -p option is defined. */
rec->opts.ignore_missing_thread = rec->opts.target.pid;
evlist__warn_user_requested_cpus(rec->evlist, rec->opts.target.cpu_list);

27
tools/perf/builtin-report.c
View File

@@ -447,7 +447,7 @@ static int report__setup_sample_type(struct report *rep)
}
}
callchain_param_setup(sample_type, perf_env__arch(&rep->session->header.env));
callchain_param_setup(sample_type, perf_env__arch(perf_session__env(rep->session)));
if (rep->stitch_lbr && (callchain_param.record_mode != CALLCHAIN_LBR)) {
ui__warning("Can't find LBR callchain. Switch off --stitch-lbr.\n"
@@ -550,7 +550,7 @@ static int evlist__tui_block_hists_browse(struct evlist *evlist, struct report *
evlist__for_each_entry(evlist, pos) {
ret = report__browse_block_hists(&rep->block_reports[i++].hist,
rep->min_percent, pos,
&rep->session->header.env);
perf_session__env(rep->session));
if (ret != 0)
return ret;
}
@@ -685,7 +685,7 @@ static int report__browse_hists(struct report *rep)
}
ret = evlist__tui_browse_hists(evlist, help, NULL, rep->min_percent,
&session->header.env, true);
perf_session__env(session), true);
/*
* Usually "ret" is the last pressed key, and we only
* care if the key notifies us to switch data file.
@@ -861,17 +861,24 @@ static int maps__fprintf_task_cb(struct map *map, void *data)
struct maps__fprintf_task_args *args = data;
const struct dso *dso = map__dso(map);
u32 prot = map__prot(map);
const struct dso_id *dso_id = dso__id_const(dso);
int ret;
char buf[SBUILD_ID_SIZE];
if (dso_id->mmap2_valid)
snprintf(buf, sizeof(buf), "%" PRIu64, dso_id->ino);
else
build_id__snprintf(&dso_id->build_id, buf, sizeof(buf));
ret = fprintf(args->fp,
"%*s %" PRIx64 "-%" PRIx64 " %c%c%c%c %08" PRIx64 " %" PRIu64 " %s\n",
"%*s %" PRIx64 "-%" PRIx64 " %c%c%c%c %08" PRIx64 " %s %s\n",
args->indent, "", map__start(map), map__end(map),
prot & PROT_READ ? 'r' : '-',
prot & PROT_WRITE ? 'w' : '-',
prot & PROT_EXEC ? 'x' : '-',
map__flags(map) ? 's' : 'p',
map__pgoff(map),
dso__id_const(dso)->ino, dso__name(dso));
buf, dso__name(dso));
if (ret < 0)
return ret;
@@ -1267,6 +1274,8 @@ static int process_attr(const struct perf_tool *tool __maybe_unused,
union perf_event *event,
struct evlist **pevlist)
{
struct perf_session *session;
struct perf_env *env;
u64 sample_type;
int err;
@@ -1279,7 +1288,9 @@ static int process_attr(const struct perf_tool *tool __maybe_unused,
* on events sample_type.
*/
sample_type = evlist__combined_sample_type(*pevlist);
callchain_param_setup(sample_type, perf_env__arch((*pevlist)->env));
session = (*pevlist)->session;
env = perf_session__env(session);
callchain_param_setup(sample_type, perf_env__arch(env));
return 0;
}
@@ -1779,7 +1790,7 @@ int cmd_report(int argc, const char **argv)
}
if ((last_key != K_SWITCH_INPUT_DATA && last_key != K_RELOAD) &&
(setup_sorting(session->evlist) < 0)) {
(setup_sorting(session->evlist, perf_session__env(session)) < 0)) {
if (sort_order)
parse_options_usage(report_usage, options, "s", 1);
if (field_order)
@@ -1835,7 +1846,7 @@ int cmd_report(int argc, const char **argv)
annotation_config__init();
}
if (symbol__init(&session->header.env) < 0)
if (symbol__init(perf_session__env(session)) < 0)
goto error;
if (report.time_str) {

160
tools/perf/builtin-sched.c
View File

@@ -994,7 +994,7 @@ thread_atoms_search(struct rb_root_cached *root, struct thread *thread,
else if (cmp < 0)
node = node->rb_right;
else {
BUG_ON(thread != atoms->thread);
BUG_ON(!RC_CHK_EQUAL(thread, atoms->thread));
return atoms;
}
}
@@ -1111,6 +1111,21 @@ add_sched_in_event(struct work_atoms *atoms, u64 timestamp)
atoms->nb_atoms++;
}
static void free_work_atoms(struct work_atoms *atoms)
{
struct work_atom *atom, *tmp;
if (atoms == NULL)
return;
list_for_each_entry_safe(atom, tmp, &atoms->work_list, list) {
list_del(&atom->list);
free(atom);
}
thread__zput(atoms->thread);
free(atoms);
}
static int latency_switch_event(struct perf_sched *sched,
struct evsel *evsel,
struct perf_sample *sample,
@@ -1634,6 +1649,7 @@ static int map_switch_event(struct perf_sched *sched, struct evsel *evsel,
const char *color = PERF_COLOR_NORMAL;
char stimestamp[32];
const char *str;
int ret = -1;
BUG_ON(this_cpu.cpu >= MAX_CPUS || this_cpu.cpu < 0);
@@ -1664,17 +1680,20 @@ static int map_switch_event(struct perf_sched *sched, struct evsel *evsel,
sched_in = map__findnew_thread(sched, machine, -1, next_pid);
sched_out = map__findnew_thread(sched, machine, -1, prev_pid);
if (sched_in == NULL || sched_out == NULL)
return -1;
goto out;
tr = thread__get_runtime(sched_in);
if (tr == NULL) {
thread__put(sched_in);
return -1;
}
if (tr == NULL)
goto out;
thread__put(sched->curr_thread[this_cpu.cpu]);
thread__put(sched->curr_out_thread[this_cpu.cpu]);
sched->curr_thread[this_cpu.cpu] = thread__get(sched_in);
sched->curr_out_thread[this_cpu.cpu] = thread__get(sched_out);
ret = 0;
str = thread__comm_str(sched_in);
new_shortname = 0;
if (!tr->shortname[0]) {
@@ -1769,12 +1788,10 @@ static int map_switch_event(struct perf_sched *sched, struct evsel *evsel,
color_fprintf(stdout, color, "\n");
out:
if (sched->map.task_name)
thread__put(sched_out);
thread__put(sched_out);
thread__put(sched_in);
return 0;
return ret;
}
static int process_sched_switch_event(const struct perf_tool *tool,
@@ -1922,7 +1939,7 @@ static int perf_sched__read_events(struct perf_sched *sched)
return PTR_ERR(session);
}
symbol__init(&session->header.env);
symbol__init(perf_session__env(session));
/* prefer sched_waking if it is captured */
if (evlist__find_tracepoint_by_name(session->evlist, "sched:sched_waking"))
@@ -2018,6 +2035,16 @@ static u64 evsel__get_time(struct evsel *evsel, u32 cpu)
return r->last_time[cpu];
}
static void timehist__evsel_priv_destructor(void *priv)
{
struct evsel_runtime *r = priv;
if (r) {
free(r->last_time);
free(r);
}
}
static int comm_width = 30;
static char *timehist_get_commstr(struct thread *thread)
@@ -2174,6 +2201,11 @@ static void timehist_print_sample(struct perf_sched *sched,
printf(" ");
}
if (!thread__comm_set(thread)) {
const char *prev_comm = evsel__strval(evsel, sample, "prev_comm");
thread__set_comm(thread, prev_comm, sample->time);
}
printf(" %-*s ", comm_width, timehist_get_commstr(thread));
if (sched->show_prio)
@@ -2311,8 +2343,10 @@ static void save_task_callchain(struct perf_sched *sched,
return;
}
if (!sched->show_callchain || sample->callchain == NULL)
if (!sched->show_callchain || sample->callchain == NULL) {
thread__put(thread);
return;
}
cursor = get_tls_callchain_cursor();
@@ -2321,10 +2355,12 @@ static void save_task_callchain(struct perf_sched *sched,
if (verbose > 0)
pr_err("Failed to resolve callchain. Skipping\n");
thread__put(thread);
return;
}
callchain_cursor_commit(cursor);
thread__put(thread);
while (true) {
struct callchain_cursor_node *node;
@@ -2401,8 +2437,17 @@ static void free_idle_threads(void)
return;
for (i = 0; i < idle_max_cpu; ++i) {
if ((idle_threads[i]))
thread__delete(idle_threads[i]);
struct thread *idle = idle_threads[i];
if (idle) {
struct idle_thread_runtime *itr;
itr = thread__priv(idle);
if (itr)
thread__put(itr->last_thread);
thread__delete(idle);
}
}
free(idle_threads);
@@ -2439,7 +2484,7 @@ static struct thread *get_idle_thread(int cpu)
}
}
return idle_threads[cpu];
return thread__get(idle_threads[cpu]);
}
static void save_idle_callchain(struct perf_sched *sched,
@@ -2494,7 +2539,8 @@ static struct thread *timehist_get_thread(struct perf_sched *sched,
if (itr == NULL)
return NULL;
itr->last_thread = thread;
thread__put(itr->last_thread);
itr->last_thread = thread__get(thread);
/* copy task callchain when entering to idle */
if (evsel__intval(evsel, sample, "next_pid") == 0)
@@ -2565,6 +2611,7 @@ static void timehist_print_wakeup_event(struct perf_sched *sched,
/* show wakeup unless both awakee and awaker are filtered */
if (timehist_skip_sample(sched, thread, evsel, sample) &&
timehist_skip_sample(sched, awakened, evsel, sample)) {
thread__put(thread);
return;
}
@@ -2581,6 +2628,8 @@ static void timehist_print_wakeup_event(struct perf_sched *sched,
printf("awakened: %s", timehist_get_commstr(awakened));
printf("\n");
thread__put(thread);
}
static int timehist_sched_wakeup_ignore(const struct perf_tool *tool __maybe_unused,
@@ -2609,8 +2658,10 @@ static int timehist_sched_wakeup_event(const struct perf_tool *tool,
return -1;
tr = thread__get_runtime(thread);
if (tr == NULL)
if (tr == NULL) {
thread__put(thread);
return -1;
}
if (tr->ready_to_run == 0)
tr->ready_to_run = sample->time;
@@ -2620,6 +2671,7 @@ static int timehist_sched_wakeup_event(const struct perf_tool *tool,
!perf_time__skip_sample(&sched->ptime, sample->time))
timehist_print_wakeup_event(sched, evsel, sample, machine, thread);
thread__put(thread);
return 0;
}
@@ -2647,6 +2699,7 @@ static void timehist_print_migration_event(struct perf_sched *sched,
if (timehist_skip_sample(sched, thread, evsel, sample) &&
timehist_skip_sample(sched, migrated, evsel, sample)) {
thread__put(thread);
return;
}
@@ -2674,6 +2727,7 @@ static void timehist_print_migration_event(struct perf_sched *sched,
printf(" cpu %d => %d", ocpu, dcpu);
printf("\n");
thread__put(thread);
}
static int timehist_migrate_task_event(const struct perf_tool *tool,
@@ -2693,8 +2747,10 @@ static int timehist_migrate_task_event(const struct perf_tool *tool,
return -1;
tr = thread__get_runtime(thread);
if (tr == NULL)
if (tr == NULL) {
thread__put(thread);
return -1;
}
tr->migrations++;
tr->migrated = sample->time;
@@ -2704,6 +2760,7 @@ static int timehist_migrate_task_event(const struct perf_tool *tool,
timehist_print_migration_event(sched, evsel, sample,
machine, thread);
}
thread__put(thread);
return 0;
}
@@ -2726,10 +2783,10 @@ static void timehist_update_task_prio(struct evsel *evsel,
return;
tr = thread__get_runtime(thread);
if (tr == NULL)
return;
if (tr != NULL)
tr->prio = next_prio;
tr->prio = next_prio;
thread__put(thread);
}
static int timehist_sched_change_event(const struct perf_tool *tool,
@@ -2741,7 +2798,7 @@ static int timehist_sched_change_event(const struct perf_tool *tool,
struct perf_sched *sched = container_of(tool, struct perf_sched, tool);
struct perf_time_interval *ptime = &sched->ptime;
struct addr_location al;
struct thread *thread;
struct thread *thread = NULL;
struct thread_runtime *tr = NULL;
u64 tprev, t = sample->time;
int rc = 0;
@@ -2865,6 +2922,7 @@ static int timehist_sched_change_event(const struct perf_tool *tool,
evsel__save_time(evsel, sample->time, sample->cpu);
thread__put(thread);
addr_location__exit(&al);
return rc;
}
@@ -3236,6 +3294,7 @@ static int perf_sched__timehist(struct perf_sched *sched)
};
struct perf_session *session;
struct perf_env *env;
struct evlist *evlist;
int err = -1;
@@ -3260,6 +3319,7 @@ static int perf_sched__timehist(struct perf_sched *sched)
if (IS_ERR(session))
return PTR_ERR(session);
env = perf_session__env(session);
if (cpu_list) {
err = perf_session__cpu_bitmap(session, cpu_list, cpu_bitmap);
if (err < 0)
@@ -3268,7 +3328,7 @@ static int perf_sched__timehist(struct perf_sched *sched)
evlist = session->evlist;
symbol__init(&session->header.env);
symbol__init(env);
if (perf_time__parse_str(&sched->ptime, sched->time_str) != 0) {
pr_err("Invalid time string\n");
@@ -3286,6 +3346,8 @@ static int perf_sched__timehist(struct perf_sched *sched)
setup_pager();
evsel__set_priv_destructor(timehist__evsel_priv_destructor);
/* prefer sched_waking if it is captured */
if (evlist__find_tracepoint_by_name(session->evlist, "sched:sched_waking"))
handlers[1].handler = timehist_sched_wakeup_ignore;
@@ -3305,7 +3367,7 @@ static int perf_sched__timehist(struct perf_sched *sched)
goto out;
/* pre-allocate struct for per-CPU idle stats */
sched->max_cpu.cpu = session->header.env.nr_cpus_online;
sched->max_cpu.cpu = env->nr_cpus_online;
if (sched->max_cpu.cpu == 0)
sched->max_cpu.cpu = 4;
if (init_idle_threads(sched->max_cpu.cpu))
@@ -3386,13 +3448,13 @@ static void __merge_work_atoms(struct rb_root_cached *root, struct work_atoms *d
this->total_runtime += data->total_runtime;
this->nb_atoms += data->nb_atoms;
this->total_lat += data->total_lat;
list_splice(&data->work_list, &this->work_list);
list_splice_init(&data->work_list, &this->work_list);
if (this->max_lat < data->max_lat) {
this->max_lat = data->max_lat;
this->max_lat_start = data->max_lat_start;
this->max_lat_end = data->max_lat_end;
}
zfree(&data);
free_work_atoms(data);
return;
}
}
@@ -3471,7 +3533,6 @@ static int perf_sched__lat(struct perf_sched *sched)
work_list = rb_entry(next, struct work_atoms, node);
output_lat_thread(sched, work_list);
next = rb_next(next);
thread__zput(work_list->thread);
}
printf(" -----------------------------------------------------------------------------------------------------------------\n");
@@ -3485,6 +3546,13 @@ static int perf_sched__lat(struct perf_sched *sched)
rc = 0;
while ((next = rb_first_cached(&sched->sorted_atom_root))) {
struct work_atoms *data;
data = rb_entry(next, struct work_atoms, node);
rb_erase_cached(next, &sched->sorted_atom_root);
free_work_atoms(data);
}
out_free_cpus_switch_event:
free_cpus_switch_event(sched);
return rc;
@@ -3556,10 +3624,10 @@ static int perf_sched__map(struct perf_sched *sched)
sched->curr_out_thread = calloc(MAX_CPUS, sizeof(*(sched->curr_out_thread)));
if (!sched->curr_out_thread)
return rc;
goto out_free_curr_thread;
if (setup_cpus_switch_event(sched))
goto out_free_curr_thread;
goto out_free_curr_out_thread;
if (setup_map_cpus(sched))
goto out_free_cpus_switch_event;
@@ -3590,7 +3658,14 @@ static int perf_sched__map(struct perf_sched *sched)
out_free_cpus_switch_event:
free_cpus_switch_event(sched);
out_free_curr_out_thread:
for (int i = 0; i < MAX_CPUS; i++)
thread__put(sched->curr_out_thread[i]);
zfree(&sched->curr_out_thread);
out_free_curr_thread:
for (int i = 0; i < MAX_CPUS; i++)
thread__put(sched->curr_thread[i]);
zfree(&sched->curr_thread);
return rc;
}
@@ -3898,13 +3973,15 @@ int cmd_sched(int argc, const char **argv)
if (!argc)
usage_with_options(sched_usage, sched_options);
thread__set_priv_destructor(free);
/*
* Aliased to 'perf script' for now:
*/
if (!strcmp(argv[0], "script")) {
return cmd_script(argc, argv);
ret = cmd_script(argc, argv);
} else if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) {
return __cmd_record(argc, argv);
ret = __cmd_record(argc, argv);
} else if (strlen(argv[0]) > 2 && strstarts("latency", argv[0])) {
sched.tp_handler = &lat_ops;
if (argc > 1) {
@@ -3913,7 +3990,7 @@ int cmd_sched(int argc, const char **argv)
usage_with_options(latency_usage, latency_options);
}
setup_sorting(&sched, latency_options, latency_usage);
return perf_sched__lat(&sched);
ret = perf_sched__lat(&sched);
} else if (!strcmp(argv[0], "map")) {
if (argc) {
argc = parse_options(argc, argv, map_options, map_usage, 0);
@@ -3924,13 +4001,14 @@ int cmd_sched(int argc, const char **argv)
sched.map.task_names = strlist__new(sched.map.task_name, NULL);
if (sched.map.task_names == NULL) {
fprintf(stderr, "Failed to parse task names\n");
return -1;
ret = -1;
goto out;
}
}
}
sched.tp_handler = &map_ops;
setup_sorting(&sched, latency_options, latency_usage);
return perf_sched__map(&sched);
ret = perf_sched__map(&sched);
} else if (strlen(argv[0]) > 2 && strstarts("replay", argv[0])) {
sched.tp_handler = &replay_ops;
if (argc) {
@@ -3938,7 +4016,7 @@ int cmd_sched(int argc, const char **argv)
if (argc)
usage_with_options(replay_usage, replay_options);
}
return perf_sched__replay(&sched);
ret = perf_sched__replay(&sched);
} else if (!strcmp(argv[0], "timehist")) {
if (argc) {
argc = parse_options(argc, argv, timehist_options,
@@ -3954,19 +4032,19 @@ int cmd_sched(int argc, const char **argv)
parse_options_usage(NULL, timehist_options, "w", true);
if (sched.show_next)
parse_options_usage(NULL, timehist_options, "n", true);
return -EINVAL;
ret = -EINVAL;
goto out;
}
ret = symbol__validate_sym_arguments();
if (ret)
return ret;
return perf_sched__timehist(&sched);
if (!ret)
ret = perf_sched__timehist(&sched);
} else {
usage_with_options(sched_usage, sched_options);
}
out:
/* free usage string allocated by parse_options_subcommand */
free((void *)sched_usage[0]);
return 0;
return ret;
}

36
tools/perf/builtin-script.c
View File

@@ -38,6 +38,7 @@
#include "print_insn.h"
#include "archinsn.h"
#include <linux/bitmap.h>
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/stringify.h>
#include <linux/time64.h>
@@ -50,6 +51,7 @@
#include <errno.h>
#include <inttypes.h>
#include <signal.h>
#include <stdio.h>
#include <sys/param.h>
#include <sys/types.h>
#include <sys/stat.h>
@@ -712,7 +714,7 @@ static int perf_session__check_output_opt(struct perf_session *session)
}
}
if (tod && !session->header.env.clock.enabled) {
if (tod && !perf_session__env(session)->clock.enabled) {
pr_err("Can't provide 'tod' time, missing clock data. "
"Please record with -k/--clockid option.\n");
return -1;
@@ -757,7 +759,7 @@ tod_scnprintf(struct perf_script *script, char *buf, int buflen,
if (buflen < 64 || !script)
return buf;
env = &script->session->header.env;
env = perf_session__env(script->session);
if (!env->clock.enabled) {
scnprintf(buf, buflen, "disabled");
return buf;
@@ -2134,8 +2136,7 @@ static void perf_sample__fprint_metric(struct perf_script *script,
perf_stat__print_shadow_stats(&stat_config, ev2,
evsel_script(ev2)->val,
sample->cpu,
&ctx,
NULL);
&ctx);
}
evsel_script(leader)->gnum = 0;
}
@@ -2251,7 +2252,7 @@ static void process_event(struct perf_script *script,
fprintf(fp, "%16" PRIu16, sample->ins_lat);
if (PRINT_FIELD(RETIRE_LAT))
fprintf(fp, "%16" PRIu16, sample->retire_lat);
fprintf(fp, "%16" PRIu16, sample->weight3);
if (PRINT_FIELD(CGROUP)) {
const char *cgrp_name;
@@ -2533,7 +2534,7 @@ static int process_attr(const struct perf_tool *tool, union perf_event *event,
* on events sample_type.
*/
sample_type = evlist__combined_sample_type(evlist);
callchain_param_setup(sample_type, perf_env__arch((*pevlist)->env));
callchain_param_setup(sample_type, perf_env__arch(perf_session__env(scr->session)));
/* Enable fields for callchain entries */
if (symbol_conf.use_callchain &&
@@ -2755,6 +2756,14 @@ process_bpf_events(const struct perf_tool *tool __maybe_unused,
sample->tid);
}
static int
process_bpf_metadata_event(struct perf_session *session __maybe_unused,
union perf_event *event)
{
perf_event__fprintf(event, NULL, stdout);
return 0;
}
static int process_text_poke_events(const struct perf_tool *tool,
union perf_event *event,
struct perf_sample *sample,
@@ -2877,8 +2886,9 @@ static int __cmd_script(struct perf_script *script)
script->tool.finished_round = process_finished_round_event;
}
if (script->show_bpf_events) {
script->tool.ksymbol = process_bpf_events;
script->tool.bpf = process_bpf_events;
script->tool.ksymbol = process_bpf_events;
script->tool.bpf = process_bpf_events;
script->tool.bpf_metadata = process_bpf_metadata_event;
}
if (script->show_text_poke_events) {
script->tool.ksymbol = process_bpf_events;
@@ -3853,6 +3863,7 @@ int cmd_script(int argc, const char **argv)
"perf script [<options>] <top-script> [script-args]",
NULL
};
struct perf_env *env;
perf_set_singlethreaded();
@@ -4099,6 +4110,7 @@ int cmd_script(int argc, const char **argv)
if (IS_ERR(session))
return PTR_ERR(session);
env = perf_session__env(session);
if (header || header_only) {
script.tool.show_feat_hdr = SHOW_FEAT_HEADER;
perf_session__fprintf_info(session, stdout, show_full_info);
@@ -4108,17 +4120,17 @@ int cmd_script(int argc, const char **argv)
if (show_full_info)
script.tool.show_feat_hdr = SHOW_FEAT_HEADER_FULL_INFO;
if (symbol__init(&session->header.env) < 0)
if (symbol__init(env) < 0)
goto out_delete;
uname(&uts);
if (data.is_pipe) { /* Assume pipe_mode indicates native_arch */
native_arch = true;
} else if (session->header.env.arch) {
if (!strcmp(uts.machine, session->header.env.arch))
} else if (env->arch) {
if (!strcmp(uts.machine, env->arch))
native_arch = true;
else if (!strcmp(uts.machine, "x86_64") &&
!strcmp(session->header.env.arch, "i386"))
!strcmp(env->arch, "i386"))
native_arch = true;
}

61
tools/perf/builtin-stat.c
View File

@@ -108,9 +108,7 @@ static struct parse_events_option_args parse_events_option_args = {
static bool all_counters_use_bpf = true;
static struct target target = {
.uid = UINT_MAX,
};
static struct target target;
static volatile sig_atomic_t child_pid = -1;
static int detailed_run = 0;
@@ -1367,7 +1365,7 @@ static struct aggr_cpu_id perf_stat__get_aggr(struct perf_stat_config *config,
struct aggr_cpu_id id;
/* per-process mode - should use global aggr mode */
if (cpu.cpu == -1)
if (cpu.cpu == -1 || cpu.cpu >= config->cpus_aggr_map->nr)
return get_id(config, cpu);
if (aggr_cpu_id__is_empty(&config->cpus_aggr_map->map[cpu.cpu]))
@@ -1515,11 +1513,8 @@ static int perf_stat_init_aggr_mode(void)
* taking the highest cpu number to be the size of
* the aggregation translate cpumap.
*/
if (!perf_cpu_map__is_any_cpu_or_is_empty(evsel_list->core.user_requested_cpus))
nr = perf_cpu_map__max(evsel_list->core.user_requested_cpus).cpu;
else
nr = 0;
stat_config.cpus_aggr_map = cpu_aggr_map__empty_new(nr + 1);
nr = perf_cpu_map__max(evsel_list->core.all_cpus).cpu + 1;
stat_config.cpus_aggr_map = cpu_aggr_map__empty_new(nr);
return stat_config.cpus_aggr_map ? 0 : -ENOMEM;
}
@@ -1694,48 +1689,48 @@ static struct aggr_cpu_id perf_env__get_global_aggr_by_cpu(struct perf_cpu cpu _
static struct aggr_cpu_id perf_stat__get_socket_file(struct perf_stat_config *config __maybe_unused,
struct perf_cpu cpu)
{
return perf_env__get_socket_aggr_by_cpu(cpu, &perf_stat.session->header.env);
return perf_env__get_socket_aggr_by_cpu(cpu, perf_session__env(perf_stat.session));
}
static struct aggr_cpu_id perf_stat__get_die_file(struct perf_stat_config *config __maybe_unused,
struct perf_cpu cpu)
{
return perf_env__get_die_aggr_by_cpu(cpu, &perf_stat.session->header.env);
return perf_env__get_die_aggr_by_cpu(cpu, perf_session__env(perf_stat.session));
}
static struct aggr_cpu_id perf_stat__get_cluster_file(struct perf_stat_config *config __maybe_unused,
struct perf_cpu cpu)
{
return perf_env__get_cluster_aggr_by_cpu(cpu, &perf_stat.session->header.env);
return perf_env__get_cluster_aggr_by_cpu(cpu, perf_session__env(perf_stat.session));
}
static struct aggr_cpu_id perf_stat__get_cache_file(struct perf_stat_config *config __maybe_unused,
struct perf_cpu cpu)
{
return perf_env__get_cache_aggr_by_cpu(cpu, &perf_stat.session->header.env);
return perf_env__get_cache_aggr_by_cpu(cpu, perf_session__env(perf_stat.session));
}
static struct aggr_cpu_id perf_stat__get_core_file(struct perf_stat_config *config __maybe_unused,
struct perf_cpu cpu)
{
return perf_env__get_core_aggr_by_cpu(cpu, &perf_stat.session->header.env);
return perf_env__get_core_aggr_by_cpu(cpu, perf_session__env(perf_stat.session));
}
static struct aggr_cpu_id perf_stat__get_cpu_file(struct perf_stat_config *config __maybe_unused,
struct perf_cpu cpu)
{
return perf_env__get_cpu_aggr_by_cpu(cpu, &perf_stat.session->header.env);
return perf_env__get_cpu_aggr_by_cpu(cpu, perf_session__env(perf_stat.session));
}
static struct aggr_cpu_id perf_stat__get_node_file(struct perf_stat_config *config __maybe_unused,
struct perf_cpu cpu)
{
return perf_env__get_node_aggr_by_cpu(cpu, &perf_stat.session->header.env);
return perf_env__get_node_aggr_by_cpu(cpu, perf_session__env(perf_stat.session));
}
static struct aggr_cpu_id perf_stat__get_global_file(struct perf_stat_config *config __maybe_unused,
struct perf_cpu cpu)
{
return perf_env__get_global_aggr_by_cpu(cpu, &perf_stat.session->header.env);
return perf_env__get_global_aggr_by_cpu(cpu, perf_session__env(perf_stat.session));
}
static aggr_cpu_id_get_t aggr_mode__get_aggr_file(enum aggr_mode aggr_mode)
@@ -1794,7 +1789,7 @@ static aggr_get_id_t aggr_mode__get_id_file(enum aggr_mode aggr_mode)
static int perf_stat_init_aggr_mode_file(struct perf_stat *st)
{
struct perf_env *env = &st->session->header.env;
struct perf_env *env = perf_session__env(st->session);
aggr_cpu_id_get_t get_id = aggr_mode__get_aggr_file(stat_config.aggr_mode);
bool needs_sort = stat_config.aggr_mode != AGGR_NONE;
@@ -1865,8 +1860,7 @@ static int add_default_events(void)
stat_config.metric_no_threshold,
stat_config.user_requested_cpu_list,
stat_config.system_wide,
stat_config.hardware_aware_grouping,
&stat_config.metric_events);
stat_config.hardware_aware_grouping);
goto out;
}
@@ -1903,8 +1897,7 @@ static int add_default_events(void)
stat_config.metric_no_threshold,
stat_config.user_requested_cpu_list,
stat_config.system_wide,
stat_config.hardware_aware_grouping,
&stat_config.metric_events);
stat_config.hardware_aware_grouping);
goto out;
}
@@ -1941,8 +1934,7 @@ static int add_default_events(void)
/*metric_no_threshold=*/true,
stat_config.user_requested_cpu_list,
stat_config.system_wide,
stat_config.hardware_aware_grouping,
&stat_config.metric_events) < 0) {
stat_config.hardware_aware_grouping) < 0) {
ret = -1;
goto out;
}
@@ -1991,8 +1983,7 @@ static int add_default_events(void)
/*metric_no_threshold=*/true,
stat_config.user_requested_cpu_list,
stat_config.system_wide,
stat_config.hardware_aware_grouping,
&stat_config.metric_events) < 0) {
stat_config.hardware_aware_grouping) < 0) {
ret = -1;
goto out;
}
@@ -2001,6 +1992,9 @@ static int add_default_events(void)
evsel->default_metricgroup = true;
evlist__splice_list_tail(evlist, &metric_evlist->core.entries);
metricgroup__copy_metric_events(evlist, /*cgrp=*/NULL,
&evlist->metric_events,
&metric_evlist->metric_events);
evlist__delete(metric_evlist);
}
}
@@ -2055,6 +2049,9 @@ static int add_default_events(void)
}
parse_events_error__exit(&err);
evlist__splice_list_tail(evsel_list, &evlist->core.entries);
metricgroup__copy_metric_events(evsel_list, /*cgrp=*/NULL,
&evsel_list->metric_events,
&evlist->metric_events);
evlist__delete(evlist);
return ret;
}
@@ -2115,8 +2112,9 @@ static int process_stat_round_event(struct perf_session *session,
{
struct perf_record_stat_round *stat_round = &event->stat_round;
struct timespec tsh, *ts = NULL;
const char **argv = session->header.env.cmdline_argv;
int argc = session->header.env.nr_cmdline;
struct perf_env *env = perf_session__env(session);
const char **argv = env->cmdline_argv;
int argc = env->nr_cmdline;
process_counters();
@@ -2741,8 +2739,7 @@ int cmd_stat(int argc, const char **argv)
stat_config.metric_no_threshold,
stat_config.user_requested_cpu_list,
stat_config.system_wide,
stat_config.hardware_aware_grouping,
&stat_config.metric_events);
stat_config.hardware_aware_grouping);
zfree(&metrics);
if (ret) {
@@ -2762,8 +2759,7 @@ int cmd_stat(int argc, const char **argv)
goto out;
}
if (evlist__expand_cgroup(evsel_list, stat_config.cgroup_list,
&stat_config.metric_events, true) < 0) {
if (evlist__expand_cgroup(evsel_list, stat_config.cgroup_list, true) < 0) {
parse_options_usage(stat_usage, stat_options,
"for-each-cgroup", 0);
goto out;
@@ -2938,7 +2934,6 @@ int cmd_stat(int argc, const char **argv)
evlist__delete(evsel_list);
metricgroup__rblist_exit(&stat_config.metric_events);
evlist__close_control(stat_config.ctl_fd, stat_config.ctl_fd_ack, &stat_config.ctl_fd_close);
return status;

2
tools/perf/builtin-timechart.c
View File

@@ -1618,7 +1618,7 @@ static int __cmd_timechart(struct timechart *tchart, const char *output_name)
if (IS_ERR(session))
return PTR_ERR(session);
symbol__init(&session->header.env);
symbol__init(perf_session__env(session));
(void)perf_header__process_sections(&session->header,
perf_data__fd(session->data),

88
tools/perf/builtin-top.c
View File

@@ -643,11 +643,12 @@ static void *display_thread_tui(void *arg)
*/
evlist__for_each_entry(top->evlist, pos) {
struct hists *hists = evsel__hists(pos);
hists->uid_filter_str = top->record_opts.target.uid_str;
hists->uid_filter_str = top->uid_str;
}
ret = evlist__tui_browse_hists(top->evlist, help, &hbt, top->min_percent,
&top->session->header.env, !top->record_opts.overwrite);
perf_session__env(top->session),
!top->record_opts.overwrite);
if (ret == K_RELOAD) {
top->zero = true;
goto repeat;
@@ -1253,7 +1254,7 @@ static int __cmd_top(struct perf_top *top)
int ret;
if (!annotate_opts.objdump_path) {
ret = perf_env__lookup_objdump(&top->session->header.env,
ret = perf_env__lookup_objdump(perf_session__env(top->session),
&annotate_opts.objdump_path);
if (ret)
return ret;
@@ -1300,7 +1301,7 @@ static int __cmd_top(struct perf_top *top)
perf_set_multithreaded();
if (perf_hpp_list.socket) {
ret = perf_env__read_cpu_topology_map(&perf_env);
ret = perf_env__read_cpu_topology_map(perf_session__env(top->session));
if (ret < 0) {
char errbuf[BUFSIZ];
const char *err = str_error_r(-ret, errbuf, sizeof(errbuf));
@@ -1571,7 +1572,7 @@ int cmd_top(int argc, const char **argv)
"Add prefix to source file path names in programs (with --prefix-strip)"),
OPT_STRING(0, "prefix-strip", &annotate_opts.prefix_strip, "N",
"Strip first N entries of source file path name in programs (with --prefix)"),
OPT_STRING('u', "uid", &target->uid_str, "user", "user to profile"),
OPT_STRING('u', "uid", &top.uid_str, "user", "user to profile"),
OPT_CALLBACK(0, "percent-limit", &top, "percent",
"Don't show entries under that percent", parse_percent_limit),
OPT_CALLBACK(0, "percentage", NULL, "relative|absolute",
@@ -1623,6 +1624,7 @@ int cmd_top(int argc, const char **argv)
NULL
};
int status = hists__init();
struct perf_env host_env;
if (status < 0)
return status;
@@ -1636,14 +1638,19 @@ int cmd_top(int argc, const char **argv)
if (top.evlist == NULL)
return -ENOMEM;
perf_env__init(&host_env);
status = perf_config(perf_top_config, &top);
if (status)
return status;
goto out_delete_evlist;
/*
* Since the per arch annotation init routine may need the cpuid, read
* it here, since we are not getting this from the perf.data header.
*/
status = perf_env__read_cpuid(&perf_env);
status = perf_env__set_cmdline(&host_env, argc, argv);
if (status)
goto out_delete_evlist;
status = perf_env__read_cpuid(&host_env);
if (status) {
/*
* Some arches do not provide a get_cpuid(), so just use pr_debug, otherwise
@@ -1653,7 +1660,6 @@ int cmd_top(int argc, const char **argv)
"Couldn't read the cpuid for this machine: %s\n",
str_error_r(errno, errbuf, sizeof(errbuf)));
}
top.evlist->env = &perf_env;
argc = parse_options(argc, argv, options, top_usage, 0);
if (argc)
@@ -1661,18 +1667,24 @@ int cmd_top(int argc, const char **argv)
if (disassembler_style) {
annotate_opts.disassembler_style = strdup(disassembler_style);
if (!annotate_opts.disassembler_style)
return -ENOMEM;
if (!annotate_opts.disassembler_style) {
status = -ENOMEM;
goto out_delete_evlist;
}
}
if (objdump_path) {
annotate_opts.objdump_path = strdup(objdump_path);
if (!annotate_opts.objdump_path)
return -ENOMEM;
if (!annotate_opts.objdump_path) {
status = -ENOMEM;
goto out_delete_evlist;
}
}
if (addr2line_path) {
symbol_conf.addr2line_path = strdup(addr2line_path);
if (!symbol_conf.addr2line_path)
return -ENOMEM;
if (!symbol_conf.addr2line_path) {
status = -ENOMEM;
goto out_delete_evlist;
}
}
status = symbol__validate_sym_arguments();
@@ -1734,6 +1746,14 @@ int cmd_top(int argc, const char **argv)
if (opts->branch_stack && callchain_param.enabled)
symbol_conf.show_branchflag_count = true;
if (opts->branch_stack) {
status = perf_env__read_core_pmu_caps(&host_env);
if (status) {
pr_err("PMU capability data is not available\n");
goto out_delete_evlist;
}
}
sort__mode = SORT_MODE__TOP;
/* display thread wants entries to be collapsed in a different tree */
perf_hpp_list.need_collapse = 1;
@@ -1747,7 +1767,17 @@ int cmd_top(int argc, const char **argv)
setup_browser(false);
if (setup_sorting(top.evlist) < 0) {
top.session = __perf_session__new(/*data=*/NULL, /*tool=*/NULL,
/*trace_event_repipe=*/false,
&host_env);
if (IS_ERR(top.session)) {
status = PTR_ERR(top.session);
top.session = NULL;
goto out_delete_evlist;
}
top.evlist->session = top.session;
if (setup_sorting(top.evlist, perf_session__env(top.session)) < 0) {
if (sort_order)
parse_options_usage(top_usage, options, "s", 1);
if (field_order)
@@ -1762,15 +1792,17 @@ int cmd_top(int argc, const char **argv)
ui__warning("%s\n", errbuf);
}
status = target__parse_uid(target);
if (status) {
int saved_errno = errno;
if (top.uid_str) {
uid_t uid = parse_uid(top.uid_str);
target__strerror(target, status, errbuf, BUFSIZ);
ui__error("%s\n", errbuf);
status = -saved_errno;
goto out_delete_evlist;
if (uid == UINT_MAX) {
ui__error("Invalid User: %s", top.uid_str);
status = -EINVAL;
goto out_delete_evlist;
}
status = parse_uid_filter(top.evlist, uid);
if (status)
goto out_delete_evlist;
}
if (target__none(target))
@@ -1820,13 +1852,6 @@ int cmd_top(int argc, const char **argv)
signal(SIGWINCH, winch_sig);
}
top.session = perf_session__new(NULL, NULL);
if (IS_ERR(top.session)) {
status = PTR_ERR(top.session);
top.session = NULL;
goto out_delete_evlist;
}
if (!evlist__needs_bpf_sb_event(top.evlist))
top.record_opts.no_bpf_event = true;
@@ -1840,7 +1865,7 @@ int cmd_top(int argc, const char **argv)
goto out_delete_evlist;
}
if (evlist__add_bpf_sb_event(top.sb_evlist, &perf_env)) {
if (evlist__add_bpf_sb_event(top.sb_evlist, &host_env)) {
pr_err("Couldn't ask for PERF_RECORD_BPF_EVENT side band events.\n.");
status = -EINVAL;
goto out_delete_evlist;
@@ -1862,6 +1887,7 @@ int cmd_top(int argc, const char **argv)
evlist__delete(top.evlist);
perf_session__delete(top.session);
annotation_options__exit();
perf_env__exit(&host_env);
return status;
}

268
tools/perf/builtin-trace.c
View File

@@ -20,9 +20,6 @@
#include <bpf/bpf.h>
#include <bpf/libbpf.h>
#include <bpf/btf.h>
#ifdef HAVE_BPF_SKEL
#include "bpf_skel/augmented_raw_syscalls.skel.h"
#endif
#endif
#include "util/bpf_map.h"
#include "util/rlimit.h"
@@ -143,6 +140,7 @@ struct syscall_fmt {
};
struct trace {
struct perf_env host_env;
struct perf_tool tool;
struct {
/** Sorted sycall numbers used by the trace. */
@@ -155,9 +153,6 @@ struct trace {
*bpf_output;
} events;
} syscalls;
#ifdef HAVE_BPF_SKEL
struct augmented_raw_syscalls_bpf *skel;
#endif
#ifdef HAVE_LIBBPF_SUPPORT
struct btf *btf;
#endif
@@ -236,6 +231,7 @@ struct trace {
struct ordered_events data;
u64 last;
} oe;
const char *uid_str;
};
static void trace__load_vmlinux_btf(struct trace *trace __maybe_unused)
@@ -1123,12 +1119,14 @@ static bool syscall_arg__strtoul_btf_type(char *bf __maybe_unused, size_t size _
#define STRARRAY(name, array) \
{ .scnprintf = SCA_STRARRAY, \
.strtoul = STUL_STRARRAY, \
.parm = &strarray__##array, }
.parm = &strarray__##array, \
.show_zero = true, }
#define STRARRAY_FLAGS(name, array) \
{ .scnprintf = SCA_STRARRAY_FLAGS, \
.strtoul = STUL_STRARRAY_FLAGS, \
.parm = &strarray__##array, }
.parm = &strarray__##array, \
.show_zero = true, }
#include "trace/beauty/eventfd.c"
#include "trace/beauty/futex_op.c"
@@ -1980,17 +1978,24 @@ static char *trace__machine__resolve_kernel_addr(void *vmachine, unsigned long l
return machine__resolve_kernel_addr(vmachine, addrp, modp);
}
static int trace__symbols_init(struct trace *trace, struct evlist *evlist)
static int trace__symbols_init(struct trace *trace, int argc, const char **argv,
struct evlist *evlist)
{
int err = symbol__init(NULL);
if (err)
return err;
trace->host = machine__new_host();
if (trace->host == NULL)
return -ENOMEM;
perf_env__init(&trace->host_env);
err = perf_env__set_cmdline(&trace->host_env, argc, argv);
if (err)
goto out;
trace->host = machine__new_host(&trace->host_env);
if (trace->host == NULL) {
err = -ENOMEM;
goto out;
}
thread__set_priv_destructor(thread_trace__delete);
err = trace_event__register_resolver(trace->host, trace__machine__resolve_kernel_addr);
@@ -2001,9 +2006,10 @@ static int trace__symbols_init(struct trace *trace, struct evlist *evlist)
evlist->core.threads, trace__tool_process,
true, false, 1);
out:
if (err)
if (err) {
perf_env__exit(&trace->host_env);
symbol__exit();
}
return err;
}
@@ -2012,6 +2018,7 @@ static void trace__symbols__exit(struct trace *trace)
machine__exit(trace->host);
trace->host = NULL;
perf_env__exit(&trace->host_env);
symbol__exit();
}
@@ -2891,13 +2898,6 @@ static int trace__fprintf_callchain(struct trace *trace, struct perf_sample *sam
return sample__fprintf_callchain(sample, 38, print_opts, get_tls_callchain_cursor(), symbol_conf.bt_stop_list, trace->output);
}
static const char *errno_to_name(struct evsel *evsel, int err)
{
struct perf_env *env = evsel__env(evsel);
return perf_env__arch_strerrno(env, err);
}
static int trace__sys_exit(struct trace *trace, struct evsel *evsel,
union perf_event *event __maybe_unused,
struct perf_sample *sample)
@@ -2983,8 +2983,9 @@ static int trace__sys_exit(struct trace *trace, struct evsel *evsel,
} else if (ret < 0) {
errno_print: {
char bf[STRERR_BUFSIZE];
const char *emsg = str_error_r(-ret, bf, sizeof(bf)),
*e = errno_to_name(evsel, -ret);
struct perf_env *env = evsel__env(evsel) ?: &trace->host_env;
const char *emsg = str_error_r(-ret, bf, sizeof(bf));
const char *e = perf_env__arch_strerrno(env, err);
fprintf(trace->output, "-1 %s (%s)", e, emsg);
}
@@ -3700,7 +3701,10 @@ static int trace__set_ev_qualifier_tp_filter(struct trace *trace)
goto out;
}
#ifdef HAVE_BPF_SKEL
#ifdef HAVE_LIBBPF_SUPPORT
static struct bpf_program *unaugmented_prog;
static int syscall_arg_fmt__cache_btf_struct(struct syscall_arg_fmt *arg_fmt, struct btf *btf, char *type)
{
int id;
@@ -3718,26 +3722,8 @@ static int syscall_arg_fmt__cache_btf_struct(struct syscall_arg_fmt *arg_fmt, st
return 0;
}
static struct bpf_program *trace__find_bpf_program_by_title(struct trace *trace, const char *name)
{
struct bpf_program *pos, *prog = NULL;
const char *sec_name;
if (trace->skel->obj == NULL)
return NULL;
bpf_object__for_each_program(pos, trace->skel->obj) {
sec_name = bpf_program__section_name(pos);
if (sec_name && !strcmp(sec_name, name)) {
prog = pos;
break;
}
}
return prog;
}
static struct bpf_program *trace__find_syscall_bpf_prog(struct trace *trace, struct syscall *sc,
static struct bpf_program *trace__find_syscall_bpf_prog(struct trace *trace __maybe_unused,
struct syscall *sc,
const char *prog_name, const char *type)
{
struct bpf_program *prog;
@@ -3745,19 +3731,19 @@ static struct bpf_program *trace__find_syscall_bpf_prog(struct trace *trace, str
if (prog_name == NULL) {
char default_prog_name[256];
scnprintf(default_prog_name, sizeof(default_prog_name), "tp/syscalls/sys_%s_%s", type, sc->name);
prog = trace__find_bpf_program_by_title(trace, default_prog_name);
prog = augmented_syscalls__find_by_title(default_prog_name);
if (prog != NULL)
goto out_found;
if (sc->fmt && sc->fmt->alias) {
scnprintf(default_prog_name, sizeof(default_prog_name), "tp/syscalls/sys_%s_%s", type, sc->fmt->alias);
prog = trace__find_bpf_program_by_title(trace, default_prog_name);
prog = augmented_syscalls__find_by_title(default_prog_name);
if (prog != NULL)
goto out_found;
}
goto out_unaugmented;
}
prog = trace__find_bpf_program_by_title(trace, prog_name);
prog = augmented_syscalls__find_by_title(prog_name);
if (prog != NULL) {
out_found:
@@ -3767,7 +3753,7 @@ static struct bpf_program *trace__find_syscall_bpf_prog(struct trace *trace, str
pr_debug("Couldn't find BPF prog \"%s\" to associate with syscalls:sys_%s_%s, not augmenting it\n",
prog_name, type, sc->name);
out_unaugmented:
return trace->skel->progs.syscall_unaugmented;
return unaugmented_prog;
}
static void trace__init_syscall_bpf_progs(struct trace *trace, int e_machine, int id)
@@ -3784,13 +3770,13 @@ static void trace__init_syscall_bpf_progs(struct trace *trace, int e_machine, in
static int trace__bpf_prog_sys_enter_fd(struct trace *trace, int e_machine, int id)
{
struct syscall *sc = trace__syscall_info(trace, NULL, e_machine, id);
return sc ? bpf_program__fd(sc->bpf_prog.sys_enter) : bpf_program__fd(trace->skel->progs.syscall_unaugmented);
return sc ? bpf_program__fd(sc->bpf_prog.sys_enter) : bpf_program__fd(unaugmented_prog);
}
static int trace__bpf_prog_sys_exit_fd(struct trace *trace, int e_machine, int id)
{
struct syscall *sc = trace__syscall_info(trace, NULL, e_machine, id);
return sc ? bpf_program__fd(sc->bpf_prog.sys_exit) : bpf_program__fd(trace->skel->progs.syscall_unaugmented);
return sc ? bpf_program__fd(sc->bpf_prog.sys_exit) : bpf_program__fd(unaugmented_prog);
}
static int trace__bpf_sys_enter_beauty_map(struct trace *trace, int e_machine, int key, unsigned int *beauty_array)
@@ -3900,7 +3886,7 @@ static struct bpf_program *trace__find_usable_bpf_prog_entry(struct trace *trace
bool is_candidate = false;
if (pair == NULL || pair->id == sc->id ||
pair->bpf_prog.sys_enter == trace->skel->progs.syscall_unaugmented)
pair->bpf_prog.sys_enter == unaugmented_prog)
continue;
for (field = sc->args, candidate_field = pair->args;
@@ -3966,7 +3952,7 @@ static struct bpf_program *trace__find_usable_bpf_prog_entry(struct trace *trace
*/
if (pair_prog == NULL) {
pair_prog = trace__find_syscall_bpf_prog(trace, pair, pair->fmt ? pair->fmt->bpf_prog_name.sys_enter : NULL, "enter");
if (pair_prog == trace->skel->progs.syscall_unaugmented)
if (pair_prog == unaugmented_prog)
goto next_candidate;
}
@@ -3982,12 +3968,17 @@ static struct bpf_program *trace__find_usable_bpf_prog_entry(struct trace *trace
static int trace__init_syscalls_bpf_prog_array_maps(struct trace *trace, int e_machine)
{
int map_enter_fd = bpf_map__fd(trace->skel->maps.syscalls_sys_enter);
int map_exit_fd = bpf_map__fd(trace->skel->maps.syscalls_sys_exit);
int beauty_map_fd = bpf_map__fd(trace->skel->maps.beauty_map_enter);
int map_enter_fd;
int map_exit_fd;
int beauty_map_fd;
int err = 0;
unsigned int beauty_array[6];
if (augmented_syscalls__get_map_fds(&map_enter_fd, &map_exit_fd, &beauty_map_fd) < 0)
return -1;
unaugmented_prog = augmented_syscalls__unaugmented();
for (int i = 0, num_idx = syscalltbl__num_idx(e_machine); i < num_idx; ++i) {
int prog_fd, key = syscalltbl__id_at_idx(e_machine, i);
@@ -4057,7 +4048,7 @@ static int trace__init_syscalls_bpf_prog_array_maps(struct trace *trace, int e_m
* For now we're just reusing the sys_enter prog, and if it
* already has an augmenter, we don't need to find one.
*/
if (sc->bpf_prog.sys_enter != trace->skel->progs.syscall_unaugmented)
if (sc->bpf_prog.sys_enter != unaugmented_prog)
continue;
/*
@@ -4082,7 +4073,13 @@ static int trace__init_syscalls_bpf_prog_array_maps(struct trace *trace, int e_m
return err;
}
#endif // HAVE_BPF_SKEL
#else // !HAVE_LIBBPF_SUPPORT
static int trace__init_syscalls_bpf_prog_array_maps(struct trace *trace __maybe_unused,
int e_machine __maybe_unused)
{
return -1;
}
#endif // HAVE_LIBBPF_SUPPORT
static int trace__set_ev_qualifier_filter(struct trace *trace)
{
@@ -4091,24 +4088,6 @@ static int trace__set_ev_qualifier_filter(struct trace *trace)
return 0;
}
static int bpf_map__set_filter_pids(struct bpf_map *map __maybe_unused,
size_t npids __maybe_unused, pid_t *pids __maybe_unused)
{
int err = 0;
#ifdef HAVE_LIBBPF_SUPPORT
bool value = true;
int map_fd = bpf_map__fd(map);
size_t i;
for (i = 0; i < npids; ++i) {
err = bpf_map_update_elem(map_fd, &pids[i], &value, BPF_ANY);
if (err)
break;
}
#endif
return err;
}
static int trace__set_filter_loop_pids(struct trace *trace)
{
unsigned int nr = 1, err;
@@ -4137,8 +4116,8 @@ static int trace__set_filter_loop_pids(struct trace *trace)
thread__put(thread);
err = evlist__append_tp_filter_pids(trace->evlist, nr, pids);
if (!err && trace->filter_pids.map)
err = bpf_map__set_filter_pids(trace->filter_pids.map, nr, pids);
if (!err)
err = augmented_syscalls__set_filter_pids(nr, pids);
return err;
}
@@ -4155,8 +4134,8 @@ static int trace__set_filter_pids(struct trace *trace)
if (trace->filter_pids.nr > 0) {
err = evlist__append_tp_filter_pids(trace->evlist, trace->filter_pids.nr,
trace->filter_pids.entries);
if (!err && trace->filter_pids.map) {
err = bpf_map__set_filter_pids(trace->filter_pids.map, trace->filter_pids.nr,
if (!err) {
err = augmented_syscalls__set_filter_pids(trace->filter_pids.nr,
trace->filter_pids.entries);
}
} else if (perf_thread_map__pid(trace->evlist->core.threads, 0) == -1) {
@@ -4412,8 +4391,8 @@ static int trace__run(struct trace *trace, int argc, const char **argv)
evlist__add(evlist, pgfault_min);
}
/* Enable ignoring missing threads when -u/-p option is defined. */
trace->opts.ignore_missing_thread = trace->opts.target.uid != UINT_MAX || trace->opts.target.pid;
/* Enable ignoring missing threads when -p option is defined. */
trace->opts.ignore_missing_thread = trace->opts.target.pid;
if (trace->sched &&
evlist__add_newtp(evlist, "sched", "sched_stat_runtime", trace__sched_stat_runtime))
@@ -4453,7 +4432,7 @@ static int trace__run(struct trace *trace, int argc, const char **argv)
goto out_delete_evlist;
}
err = trace__symbols_init(trace, evlist);
err = trace__symbols_init(trace, argc, argv, evlist);
if (err < 0) {
fprintf(trace->output, "Problems initializing symbol libraries!\n");
goto out_delete_evlist;
@@ -4479,41 +4458,18 @@ static int trace__run(struct trace *trace, int argc, const char **argv)
err = evlist__open(evlist);
if (err < 0)
goto out_error_open;
#ifdef HAVE_BPF_SKEL
if (trace->syscalls.events.bpf_output) {
struct perf_cpu cpu;
/*
* Set up the __augmented_syscalls__ BPF map to hold for each
* CPU the bpf-output event's file descriptor.
*/
perf_cpu_map__for_each_cpu(cpu, i, trace->syscalls.events.bpf_output->core.cpus) {
int mycpu = cpu.cpu;
augmented_syscalls__setup_bpf_output();
bpf_map__update_elem(trace->skel->maps.__augmented_syscalls__,
&mycpu, sizeof(mycpu),
xyarray__entry(trace->syscalls.events.bpf_output->core.fd,
mycpu, 0),
sizeof(__u32), BPF_ANY);
}
}
if (trace->skel)
trace->filter_pids.map = trace->skel->maps.pids_filtered;
#endif
err = trace__set_filter_pids(trace);
if (err < 0)
goto out_error_mem;
#ifdef HAVE_BPF_SKEL
if (trace->skel && trace->skel->progs.sys_enter) {
/*
* TODO: Initialize for all host binary machine types, not just
* those matching the perf binary.
*/
trace__init_syscalls_bpf_prog_array_maps(trace, EM_HOST);
}
#endif
/*
* TODO: Initialize for all host binary machine types, not just
* those matching the perf binary.
*/
trace__init_syscalls_bpf_prog_array_maps(trace, EM_HOST);
if (trace->ev_qualifier_ids.nr > 0) {
err = trace__set_ev_qualifier_filter(trace);
@@ -4749,7 +4705,7 @@ static int trace__replay(struct trace *trace)
if (trace->opts.target.tid)
symbol_conf.tid_list_str = strdup(trace->opts.target.tid);
if (symbol__init(&session->header.env) < 0)
if (symbol__init(perf_session__env(session)) < 0)
goto out;
trace->host = &session->machines.host;
@@ -5358,6 +5314,7 @@ static int trace__config(const char *var, const char *value, void *arg)
static void trace__exit(struct trace *trace)
{
thread__zput(trace->current);
strlist__delete(trace->ev_qualifier);
zfree(&trace->ev_qualifier_ids.entries);
if (trace->syscalls.table) {
@@ -5368,24 +5325,13 @@ static void trace__exit(struct trace *trace)
zfree(&trace->perfconfig_events);
evlist__delete(trace->evlist);
trace->evlist = NULL;
ordered_events__free(&trace->oe.data);
#ifdef HAVE_LIBBPF_SUPPORT
btf__free(trace->btf);
trace->btf = NULL;
#endif
}
#ifdef HAVE_BPF_SKEL
static int bpf__setup_bpf_output(struct evlist *evlist)
{
int err = parse_event(evlist, "bpf-output/no-inherit=1,name=__augmented_syscalls__/");
if (err)
pr_debug("ERROR: failed to create the \"__augmented_syscalls__\" bpf-output event\n");
return err;
}
#endif
int cmd_trace(int argc, const char **argv)
{
const char *trace_usage[] = {
@@ -5398,7 +5344,6 @@ int cmd_trace(int argc, const char **argv)
struct trace trace = {
.opts = {
.target = {
.uid = UINT_MAX,
.uses_mmap = true,
},
.user_freq = UINT_MAX,
@@ -5445,8 +5390,7 @@ int cmd_trace(int argc, const char **argv)
"child tasks do not inherit counters"),
OPT_CALLBACK('m', "mmap-pages", &trace.opts.mmap_pages, "pages",
"number of mmap data pages", evlist__parse_mmap_pages),
OPT_STRING('u', "uid", &trace.opts.target.uid_str, "user",
"user to profile"),
OPT_STRING('u', "uid", &trace.uid_str, "user", "user to profile"),
OPT_CALLBACK(0, "duration", &trace, "float",
"show only events with duration > N.M ms",
trace__set_duration),
@@ -5519,6 +5463,9 @@ int cmd_trace(int argc, const char **argv)
sigchld_act.sa_sigaction = sighandler_chld;
sigaction(SIGCHLD, &sigchld_act, NULL);
ordered_events__init(&trace.oe.data, ordered_events__deliver_event, &trace);
ordered_events__set_copy_on_queue(&trace.oe.data, true);
trace.evlist = evlist__new();
if (trace.evlist == NULL) {
@@ -5581,7 +5528,6 @@ int cmd_trace(int argc, const char **argv)
"cgroup monitoring only available in system-wide mode");
}
#ifdef HAVE_BPF_SKEL
if (!trace.trace_syscalls)
goto skip_augmentation;
@@ -5600,42 +5546,17 @@ int cmd_trace(int argc, const char **argv)
goto skip_augmentation;
}
trace.skel = augmented_raw_syscalls_bpf__open();
if (!trace.skel) {
pr_debug("Failed to open augmented syscalls BPF skeleton");
} else {
/*
* Disable attaching the BPF programs except for sys_enter and
* sys_exit that tail call into this as necessary.
*/
struct bpf_program *prog;
err = augmented_syscalls__prepare();
if (err < 0)
goto skip_augmentation;
bpf_object__for_each_program(prog, trace.skel->obj) {
if (prog != trace.skel->progs.sys_enter && prog != trace.skel->progs.sys_exit)
bpf_program__set_autoattach(prog, /*autoattach=*/false);
}
trace__add_syscall_newtp(&trace);
err = augmented_raw_syscalls_bpf__load(trace.skel);
err = augmented_syscalls__create_bpf_output(trace.evlist);
if (err == 0)
trace.syscalls.events.bpf_output = evlist__last(trace.evlist);
if (err < 0) {
libbpf_strerror(err, bf, sizeof(bf));
pr_debug("Failed to load augmented syscalls BPF skeleton: %s\n", bf);
} else {
augmented_raw_syscalls_bpf__attach(trace.skel);
trace__add_syscall_newtp(&trace);
}
}
err = bpf__setup_bpf_output(trace.evlist);
if (err) {
libbpf_strerror(err, bf, sizeof(bf));
pr_err("ERROR: Setup BPF output event failed: %s\n", bf);
goto out;
}
trace.syscalls.events.bpf_output = evlist__last(trace.evlist);
assert(evsel__name_is(trace.syscalls.events.bpf_output, "__augmented_syscalls__"));
skip_augmentation:
#endif
err = -1;
if (trace.trace_pgfaults) {
@@ -5677,11 +5598,6 @@ int cmd_trace(int argc, const char **argv)
trace__load_vmlinux_btf(&trace);
}
if (trace.sort_events) {
ordered_events__init(&trace.oe.data, ordered_events__deliver_event, &trace);
ordered_events__set_copy_on_queue(&trace.oe.data, true);
}
/*
* If we are augmenting syscalls, then combine what we put in the
* __augmented_syscalls__ BPF map with what is in the
@@ -5804,11 +5720,19 @@ int cmd_trace(int argc, const char **argv)
goto out_close;
}
err = target__parse_uid(&trace.opts.target);
if (err) {
target__strerror(&trace.opts.target, err, bf, sizeof(bf));
fprintf(trace.output, "%s", bf);
goto out_close;
if (trace.uid_str) {
uid_t uid = parse_uid(trace.uid_str);
if (uid == UINT_MAX) {
ui__error("Invalid User: %s", trace.uid_str);
err = -EINVAL;
goto out_close;
}
err = parse_uid_filter(trace.evlist, uid);
if (err)
goto out_close;
trace.opts.target.system_wide = true;
}
if (!argc && target__none(&trace.opts.target))
@@ -5824,8 +5748,6 @@ int cmd_trace(int argc, const char **argv)
fclose(trace.output);
out:
trace__exit(&trace);
#ifdef HAVE_BPF_SKEL
augmented_raw_syscalls_bpf__destroy(trace.skel);
#endif
augmented_syscalls__cleanup();
return err;
}

9
tools/perf/check-headers.sh
View File

@@ -4,8 +4,7 @@
YELLOW='\033[0;33m'
NC='\033[0m' # No Color
declare -a FILES
FILES=(
declare -a FILES=(
"include/uapi/linux/const.h"
"include/uapi/drm/drm.h"
"include/uapi/drm/i915_drm.h"
@@ -73,8 +72,7 @@ FILES=(
"scripts/syscall.tbl"
)
declare -a SYNC_CHECK_FILES
SYNC_CHECK_FILES=(
declare -a SYNC_CHECK_FILES=(
"arch/x86/include/asm/inat.h"
"arch/x86/include/asm/insn.h"
"arch/x86/lib/inat.c"
@@ -86,8 +84,7 @@ SYNC_CHECK_FILES=(
# tables that then gets included in .c files for things like id->string syscall
# tables (and the reverse lookup as well: string -> id)
declare -a BEAUTY_FILES
BEAUTY_FILES=(
declare -a BEAUTY_FILES=(
"arch/x86/include/asm/irq_vectors.h"
"arch/x86/include/uapi/asm/prctl.h"
"include/linux/socket.h"

2
tools/perf/include/perf/perf_dlfilter.h
View File

@@ -87,7 +87,7 @@ struct perf_dlfilter_al {
__u8 is_64_bit; /* Only valid if dso is not NULL */
__u8 is_kernel_ip; /* True if in kernel space */
__u32 buildid_size;
__u8 *buildid;
const __u8 *buildid;
/* Below members are only populated by resolve_ip() */
__u8 filtered; /* True if this sample event will be filtered out */
const char *comm;

4
tools/perf/jvmti/libjvmti.c
View File

@@ -141,11 +141,11 @@ copy_class_filename(const char * class_sign, const char * file_name, char * resu
* Assume path name is class hierarchy, this is a common practice with Java programs
*/
if (*class_sign == 'L') {
int j, i = 0;
size_t j, i = 0;
char *p = strrchr(class_sign, '/');
if (p) {
/* drop the 'L' prefix and copy up to the final '/' */
for (i = 0; i < (p - class_sign); i++)
for (i = 0; i < (size_t)(p - class_sign); i++)
result[i] = class_sign[i+1];
}
/*

35
tools/perf/perf-archive.sh
View File

@@ -16,6 +16,13 @@ while [ $# -gt 0 ] ; do
elif [ $1 == "--unpack" ]; then
UNPACK=1
shift
elif [ $1 == "--exclude-buildids" ]; then
EXCLUDE_BUILDIDS="$2"
if [ ! -e "$EXCLUDE_BUILDIDS" ]; then
echo "Provided exclude-buildids file $EXCLUDE_BUILDIDS does not exist"
exit 1
fi
shift 2
else
PERF_DATA=$1
UNPACK_TAR=$1
@@ -86,11 +93,29 @@ fi
BUILDIDS=$(mktemp /tmp/perf-archive-buildids.XXXXXX)
perf buildid-list -i $PERF_DATA --with-hits | grep -v "^ " > $BUILDIDS
if [ ! -s $BUILDIDS ] ; then
echo "perf archive: no build-ids found"
rm $BUILDIDS || true
exit 1
#
# EXCLUDE_BUILDIDS is an optional file that contains build-ids to be excluded from the
# archive. It is a list of build-ids, one per line, without any leading or trailing spaces.
# If the file is empty, all build-ids will be included in the archive. To create a exclude-
# buildids file, you can use the following command:
# perf buildid-list -i perf.data --with-hits | grep -v "^ " > exclude_buildids.txt
# You can edit the file to remove the lines that you want to keep in the archive, then:
# perf archive --exclude-buildids exclude_buildids.txt
#
if [ -s "$EXCLUDE_BUILDIDS" ]; then
perf buildid-list -i $PERF_DATA --with-hits | grep -v "^ " | grep -Fv -f $EXCLUDE_BUILDIDS > $BUILDIDS
if [ ! -s "$BUILDIDS" ] ; then
echo "perf archive: no build-ids found after applying exclude-buildids file"
rm $BUILDIDS || true
exit 1
fi
else
perf buildid-list -i $PERF_DATA --with-hits | grep -v "^ " > $BUILDIDS
if [ ! -s "$BUILDIDS" ] ; then
echo "perf archive: no build-ids found"
rm $BUILDIDS || true
exit 1
fi
fi
MANIFEST=$(mktemp /tmp/perf-archive-manifest.XXXXXX)

3
tools/perf/perf.c
View File

@@ -346,12 +346,9 @@ static int run_builtin(struct cmd_struct *p, int argc, const char **argv)
use_pager = 1;
commit_pager_choice();
perf_env__init(&perf_env);
perf_env__set_cmdline(&perf_env, argc, argv);
status = p->fn(argc, argv);
perf_config__exit();
exit_browser(status);
perf_env__exit(&perf_env);
if (status)
return status & 0xff;

70
tools/perf/pmu-events/arch/arm64/common-and-microarch.json
View File

@@ -1833,5 +1833,75 @@
"EventCode": "0x8324",
"EventName": "L1I_CACHE_REFILL_PERCYC",
"BriefDescription": "Level 1 instruction or unified cache refills in progress."
},
{
"EventCode": "0x8431",
"EventName": "ASE_FP_VREDUCE_SPEC",
"BriefDescription": "Floating-point operation_speculatively_executed, Advanced SIMD pairwise or reduction."
},
{
"EventCode": "0x8432",
"EventName": "SVE_FP_PREDUCE_SPEC",
"BriefDescription": "Floating-point operation_speculatively_executed, Advanced SIMD pairwise add step or pairwise reduce step."
},
{
"EventCode": "0x8443",
"EventName": "ASE_FP_BF16_MIN_SPEC",
"BriefDescription": "Advanced SIMD data processing operation speculatively_executed, smallest type is BFloat16 floating-point."
},
{
"EventCode": "0x8444",
"EventName": "ASE_FP_FP8_MIN_SPEC",
"BriefDescription": "Advanced SIMD data processing operation speculatively_executed, smallest type is 8-bit floating-point."
},
{
"EventCode": "0x844B",
"EventName": "ASE_SVE_FP_BF16_MIN_SPEC",
"BriefDescription": "Advanced SIMD data processing or SVE data processing operation speculatively_executed, smallest type is BFloat16 floating-point."
},
{
"EventCode": "0x844C",
"EventName": "ASE_SVE_FP_FP8_MIN_SPEC",
"BriefDescription": "Advanced SIMD data processing or SVE data processing operation speculatively_executed, smallest type is 8-bit floating-point."
},
{
"EventCode": "0x8463",
"EventName": "SVE_FP_BF16_MIN_SPEC",
"BriefDescription": "SVE data processing operation speculatively_executed, smallest type is BFloat16 floating-point."
},
{
"EventCode": "0x8464",
"EventName": "SVE_FP_FP8_MIN_SPEC",
"BriefDescription": "SVE data processing operation speculatively_executed, smallest type is 8-bit floating-point."
},
{
"EventCode": "0x8473",
"EventName": "FP_BF16_MIN_SPEC",
"BriefDescription": "Floating-point operation speculatively_executed, smallest type is BFloat16 floating-point."
},
{
"EventCode": "0x8474",
"EventName": "FP_FP8_MIN_SPEC",
"BriefDescription": "Floating-point operation speculatively_executed, smallest type is 8-bit floating-point."
},
{
"EventCode": "0x8483",
"EventName": "FP_BF16_FIXED_MIN_OPS_SPEC",
"BriefDescription": "Non-scalable element arithmetic operations speculatively executed, smallest type is BFloat16 floating-point."
},
{
"EventCode": "0x8484",
"EventName": "FP_FP8_FIXED_MIN_OPS_SPEC",
"BriefDescription": "Non-scalable element arithmetic operations speculatively executed, smallest type is 8-bit floating-point."
},
{
"EventCode": "0x848B",
"EventName": "FP_BF16_SCALE_MIN_OPS_SPEC",
"BriefDescription": "Scalable element arithmetic operations speculatively executed, smallest type is BFloat16 floating-point."
},
{
"EventCode": "0x848C",
"EventName": "FP_FP8_SCALE_MIN_OPS_SPEC",
"BriefDescription": "Scalable element arithmetic operations speculatively executed, smallest type is 8-bit floating-point."
}
]

2
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/core-imp-def.json
View File

@@ -1,6 +1,6 @@
[
{
"ArchStdEvent": "L1I_CACHE_PRF",
"BriefDescription": "This event counts fetch counted by either Level 1 instruction hardware prefetch or Level 1 instruction software prefetch."
"BriefDescription": "This event counts L1I_CACHE caused by hardware prefetch or software prefetch."
}
]

4
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/cycle_accounting.json
View File

@@ -12,12 +12,12 @@
{
"EventCode": "0x0184",
"EventName": "LD_COMP_WAIT",
"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access."
"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache, L3 cache and memory access."
},
{
"EventCode": "0x0185",
"EventName": "LD_COMP_WAIT_EX",
"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access."
"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache, L3 cache and memory access."
},
{
"EventCode": "0x0186",

2
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/exception.json
View File

@@ -33,7 +33,7 @@
},
{
"ArchStdEvent": "EXC_SMC",
"BriefDescription": "This event counts only Secure Monitor Call exceptions. The counter does not increment on SMC instructions trapped as a Hyp Trap exception."
"BriefDescription": "This event counts only Secure Monitor Call exceptions. This event does not increment on SMC instructions trapped as a Hyp Trap exception."
},
{
"ArchStdEvent": "EXC_HVC",

98
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/fp_operation.json
View File

@@ -2,7 +2,7 @@
{
"EventCode": "0x0105",
"EventName": "FP_MV_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point move operations."
"BriefDescription": "This event counts architecturally executed floating-point move operation."
},
{
"EventCode": "0x0112",
@@ -24,7 +24,7 @@
},
{
"ArchStdEvent": "ASE_SVE_FP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point operation."
},
{
"ArchStdEvent": "FP_HP_SPEC",
@@ -40,7 +40,7 @@
},
{
"ArchStdEvent": "ASE_SVE_FP_HP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE half-precision floating-point operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE half-precision floating-point operation."
},
{
"ArchStdEvent": "FP_SP_SPEC",
@@ -56,7 +56,7 @@
},
{
"ArchStdEvent": "ASE_SVE_FP_SP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE single-precision floating-point operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE single-precision floating-point operation."
},
{
"ArchStdEvent": "FP_DP_SPEC",
@@ -72,7 +72,7 @@
},
{
"ArchStdEvent": "ASE_SVE_FP_DP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE double-precision floating-point operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE double-precision floating-point operation."
},
{
"ArchStdEvent": "FP_DIV_SPEC",
@@ -88,7 +88,7 @@
},
{
"ArchStdEvent": "ASE_SVE_FP_DIV_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point divide operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point divide operation."
},
{
"ArchStdEvent": "FP_SQRT_SPEC",
@@ -104,7 +104,7 @@
},
{
"ArchStdEvent": "ASE_SVE_FP_SQRT_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point square root operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point square root operation."
},
{
"ArchStdEvent": "ASE_FP_FMA_SPEC",
@@ -116,11 +116,11 @@
},
{
"ArchStdEvent": "ASE_SVE_FP_FMA_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point FMA operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point FMA operation."
},
{
"ArchStdEvent": "FP_MUL_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point multiply operations."
"BriefDescription": "This event counts architecturally executed floating-point multiply operation."
},
{
"ArchStdEvent": "ASE_FP_MUL_SPEC",
@@ -132,11 +132,11 @@
},
{
"ArchStdEvent": "ASE_SVE_FP_MUL_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point multiply operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point multiply operation."
},
{
"ArchStdEvent": "FP_ADDSUB_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point add or subtract operations."
"BriefDescription": "This event counts architecturally executed floating-point add or subtract operation."
},
{
"ArchStdEvent": "ASE_FP_ADDSUB_SPEC",
@@ -148,19 +148,19 @@
},
{
"ArchStdEvent": "ASE_SVE_FP_ADDSUB_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point add or subtract operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point add or subtract operation."
},
{
"ArchStdEvent": "ASE_FP_RECPE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operation."
},
{
"ArchStdEvent": "SVE_FP_RECPE_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point reciprocal estimate operations."
"BriefDescription": "This event counts architecturally executed SVE floating-point reciprocal estimate operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_RECPE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point reciprocal estimate operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point reciprocal estimate operation."
},
{
"ArchStdEvent": "ASE_FP_CVT_SPEC",
@@ -172,15 +172,15 @@
},
{
"ArchStdEvent": "ASE_SVE_FP_CVT_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point convert operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point convert operation."
},
{
"ArchStdEvent": "SVE_FP_AREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point accumulating reduction operations."
"BriefDescription": "This event counts architecturally executed SVE floating-point accumulating reduction operation."
},
{
"ArchStdEvent": "ASE_FP_PREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operation."
},
{
"ArchStdEvent": "SVE_FP_VREDUCE_SPEC",
@@ -188,15 +188,15 @@
},
{
"ArchStdEvent": "ASE_SVE_FP_VREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point vector reduction operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point vector reduction operation."
},
{
"ArchStdEvent": "FP_SCALE_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed SVE arithmetic operations. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC."
"BriefDescription": "This event counts architecturally executed SVE arithmetic operation. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_FIXED_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed v8SIMD&FP arithmetic operations. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. The event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
"BriefDescription": "This event counts architecturally executed v8SIMD&FP arithmetic operation. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
},
{
"ArchStdEvent": "ASE_SVE_FP_DOT_SPEC",
@@ -205,5 +205,61 @@
{
"ArchStdEvent": "ASE_SVE_FP_MMLA_SPEC",
"BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE floating-point matrix multiply operation."
},
{
"ArchStdEvent": "ASE_FP_VREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point vector reduction operation."
},
{
"ArchStdEvent": "SVE_FP_PREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point pairwise add step operation."
},
{
"ArchStdEvent": "ASE_FP_BF16_MIN_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD data processing operations, smallest type is BFloat16 floating-point."
},
{
"ArchStdEvent": "ASE_FP_FP8_MIN_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD data processing operations, smallest type is 8-bit floating-point."
},
{
"ArchStdEvent": "ASE_SVE_FP_BF16_MIN_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD data processing or SVE data processing operations, smallest type is BFloat16 floating-point."
},
{
"ArchStdEvent": "ASE_SVE_FP_FP8_MIN_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD data processing or SVE data processing operations, smallest type is 8-bit floating-point."
},
{
"ArchStdEvent": "SVE_FP_BF16_MIN_SPEC",
"BriefDescription": "This event counts architecturally executed SVE data processing operations, smallest type is BFloat16 floating-point."
},
{
"ArchStdEvent": "SVE_FP_FP8_MIN_SPEC",
"BriefDescription": "This event counts architecturally executed SVE data processing operations, smallest type is 8-bit floating-point."
},
{
"ArchStdEvent": "FP_BF16_MIN_SPEC",
"BriefDescription": "This event counts architecturally executed data processing operations, smallest type is BFloat16 floating-point."
},
{
"ArchStdEvent": "FP_FP8_MIN_SPEC",
"BriefDescription": "This event counts architecturally executed data processing operations, smallest type is 8-bit floating-point."
},
{
"ArchStdEvent": "FP_BF16_FIXED_MIN_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed non-scalable element arithmetic operations, smallest type is BFloat16 floating-point."
},
{
"ArchStdEvent": "FP_FP8_FIXED_MIN_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed non-scalable element arithmetic operations, smallest type is 8-bit floating-point."
},
{
"ArchStdEvent": "FP_BF16_SCALE_MIN_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed scalable element arithmetic operations, smallest type is BFloat16 floating-point."
},
{
"ArchStdEvent": "FP_FP8_SCALE_MIN_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed scalable element arithmetic operations, smallest type is 8-bit floating-point."
}
]

10
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1d_cache.json
View File

@@ -72,11 +72,11 @@
},
{
"ArchStdEvent": "L1D_CACHE_HWPRF",
"BriefDescription": "This event counts access counted by L1D_CACHE that is due to a hardware prefetch."
"BriefDescription": "This event counts L1D_CACHE caused by hardware prefetch."
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_HWPRF",
"BriefDescription": "This event counts hardware prefetch counted by L1D_CACHE_HWPRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache."
"BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch."
},
{
"ArchStdEvent": "L1D_CACHE_HIT_RD",
@@ -100,14 +100,14 @@
},
{
"ArchStdEvent": "L1D_CACHE_PRF",
"BriefDescription": "This event counts fetch counted by either Level 1 data hardware prefetch or Level 1 data software prefetch."
"BriefDescription": "This event counts L1D_CACHE caused by hardware prefetch or software prefetch."
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_PRF",
"BriefDescription": "This event counts hardware prefetch counted by L1D_CACHE_PRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache."
"BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch or software prefetch."
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_PERCYC",
"BriefDescription": "The counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle."
"BriefDescription": "This counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle."
}
]

8
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1i_cache.json
View File

@@ -23,11 +23,11 @@
},
{
"ArchStdEvent": "L1I_CACHE_HWPRF",
"BriefDescription": "This event counts access counted by L1I_CACHE that is due to a hardware prefetch."
"BriefDescription": "This event counts L1I_CACHE caused by hardware prefetch."
},
{
"ArchStdEvent": "L1I_CACHE_REFILL_HWPRF",
"BriefDescription": "This event counts hardware prefetch counted by L1I_CACHE_HWPRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache."
"BriefDescription": "This event counts L1I_CACHE_REFILL caused by hardware prefetch."
},
{
"ArchStdEvent": "L1I_CACHE_HIT_RD",
@@ -43,10 +43,10 @@
},
{
"ArchStdEvent": "L1I_CACHE_REFILL_PRF",
"BriefDescription": "This event counts hardware prefetch counted by L1I_CACHE_PRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache."
"BriefDescription": "This event counts L1I_CACHE_REFILL caused by hardware prefetch or software prefetch."
},
{
"ArchStdEvent": "L1I_CACHE_REFILL_PERCYC",
"BriefDescription": "The counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle."
"BriefDescription": "This counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle."
}
]

28
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l2_cache.json
View File

@@ -21,19 +21,19 @@
},
{
"ArchStdEvent": "L2D_CACHE_RD",
"BriefDescription": "This event counts L2D CACHE caused by read access."
"BriefDescription": "This event counts L2D_CACHE caused by read access."
},
{
"ArchStdEvent": "L2D_CACHE_WR",
"BriefDescription": "This event counts L2D CACHE caused by write access."
"BriefDescription": "This event counts L2D_CACHE caused by write access."
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD",
"BriefDescription": "This event counts L2D CACHE_REFILL caused by read access."
"BriefDescription": "This event counts L2D_CACHE_REFILL caused by read access."
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR",
"BriefDescription": "This event counts L2D CACHE_REFILL caused by write access."
"BriefDescription": "This event counts L2D_CACHE_REFILL caused by write access."
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM",
@@ -57,7 +57,7 @@
{
"EventCode": "0x0305",
"EventName": "L2D_CACHE_HWPRF_ADJACENT",
"BriefDescription": "This event counts L2D_CACHE caused by hardware adjacent prefetch access."
"BriefDescription": "This event counts L2D_CACHE caused by hardware adjacent prefetch."
},
{
"EventCode": "0x0308",
@@ -111,7 +111,7 @@
},
{
"ArchStdEvent": "L2D_CACHE_LMISS_RD",
"BriefDescription": "This event counts operations that cause a refill of the L2D cache that incurs additional latency."
"BriefDescription": "This event counts operations that cause a refill of the L2 cache that incurs additional latency."
},
{
"ArchStdEvent": "L2D_CACHE_MISS",
@@ -119,23 +119,23 @@
},
{
"ArchStdEvent": "L2D_CACHE_HWPRF",
"BriefDescription": "This event counts access counted by L2D_CACHE that is due to a hardware prefetch."
"BriefDescription": "This event counts L2D_CACHE caused by hardware prefetch."
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_HWPRF",
"BriefDescription": "This event counts hardware prefetch counted by L2D_CACHE_HWPRF that causes a refill of the Level 2 cache, or any Level 1 data and instruction cache of this PE, from outside of those caches."
"BriefDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch."
},
{
"ArchStdEvent": "L2D_CACHE_HIT_RD",
"BriefDescription": "This event counts demand read counted by L2D_CACHE_RD that hits in the Level 2 data cache."
"BriefDescription": "This event counts demand read counted by L2D_CACHE_RD that hits in the Level 2 cache."
},
{
"ArchStdEvent": "L2D_CACHE_HIT_WR",
"BriefDescription": "This event counts demand write counted by L2D_CACHE_WR that hits in the Level 2 data cache."
"BriefDescription": "This event counts demand write counted by L2D_CACHE_WR that hits in the Level 2 cache."
},
{
"ArchStdEvent": "L2D_CACHE_HIT",
"BriefDescription": "This event counts access counted by L2D_CACHE that hits in the Level 2 data cache."
"BriefDescription": "This event counts access counted by L2D_CACHE that hits in the Level 2 cache."
},
{
"ArchStdEvent": "L2D_LFB_HIT_RD",
@@ -147,14 +147,14 @@
},
{
"ArchStdEvent": "L2D_CACHE_PRF",
"BriefDescription": "This event counts fetch counted by either Level 2 data hardware prefetch or Level 2 data software prefetch."
"BriefDescription": "This event counts L2D_CACHE caused by hardware prefetch or software prefetch."
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_PRF",
"BriefDescription": "This event counts hardware prefetch counted by L2D_CACHE_PRF that causes a refill of the Level 2 data cache from outside of the Level 1 data cache."
"BriefDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch or software prefetch."
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_PERCYC",
"BriefDescription": "The counter counts by the number of cache refills counted by L2D_CACHE_REFILL in progress on each Processor cycle."
"BriefDescription": "This counter counts by the number of cache refills counted by L2D_CACHE_REFILL in progress on each Processor cycle."
}
]

63
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l3_cache.json
View File

@@ -30,17 +30,17 @@
{
"EventCode": "0x0394",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_PRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by prefetch access."
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch or software prefetch."
},
{
"EventCode": "0x0395",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_HWPRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch access."
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch."
},
{
"EventCode": "0x0396",
"EventName": "L2D_CACHE_REFILL_L3D_MISS",
"BriefDescription": "This event counts operations that cause a miss of the L3 cache."
"BriefDescription": "This event counts operations that cause a miss of the L3 cache. Note: This event may count inaccurately."
},
{
"EventCode": "0x0397",
@@ -60,17 +60,17 @@
{
"EventCode": "0x039A",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by prefetch access."
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch or software prefetch. Note: This event may count inaccurately."
},
{
"EventCode": "0x039B",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_HWPRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch access."
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch. Note: This event may count inaccurately."
},
{
"EventCode": "0x039C",
"EventName": "L2D_CACHE_REFILL_L3D_HIT",
"BriefDescription": "This event counts operations that cause a hit of the L3 cache."
"BriefDescription": "This event counts operations that cause a hit of the L3 cache. Note: This event may count inaccurately."
},
{
"EventCode": "0x039D",
@@ -90,70 +90,65 @@
{
"EventCode": "0x03A0",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_PRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by prefetch access."
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch or software prefetch. Note: This event may count inaccurately."
},
{
"EventCode": "0x03A1",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_HWPRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch access."
},
{
"EventCode": "0x03A2",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT",
"BriefDescription": "This event counts the number of L3 cache misses where the requests hit the PFTGT buffer."
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch. Note: This event may count inaccurately."
},
{
"EventCode": "0x03A3",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand access."
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT",
"BriefDescription": "This event counts the number of L3 cache misses caused by demand access where the requests hit the PFTGT buffer."
},
{
"EventCode": "0x03A4",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_RD",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand read access."
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_RD_PFTGT_HIT",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT caused by read access."
},
{
"EventCode": "0x03A5",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_WR",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand write access."
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_WR_PFTGT_HIT",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT caused by write access."
},
{
"EventCode": "0x03A6",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_L_MEM",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access the memory in the same socket as the requests."
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_L_MEM",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the memory in the same socket as the requests."
},
{
"EventCode": "0x03A7",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_MEM",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access the memory in the different socket from the requests."
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_FR_MEM",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the memory in the different socket from the requests."
},
{
"EventCode": "0x03A8",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_L_L2",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access the different L2 cache from the requests in the same Numa nodes as the requests."
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_L_L2",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the different L2 cache from the requests in the same Numa nodes as the requests."
},
{
"EventCode": "0x03A9",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_NR_L2",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L2 cache in the different Numa nodes from the requests in the same socket as the requests."
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_NR_L2",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L2 cache in the different Numa nodes from the requests in the same socket as the requests."
},
{
"EventCode": "0x03AA",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_NR_L3",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L3 cache in the different Numa nodes from the requests in the same socket as the requests."
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_NR_L3",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L3 cache in the different Numa nodes from the requests in the same socket as the requests."
},
{
"EventCode": "0x03AB",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_L2",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L2 cache in the different socket from the requests."
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_FR_L2",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L2 cache in the different socket from the requests."
},
{
"EventCode": "0x03AC",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_L3",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L3 cache in the different socket from the requests."
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_FR_L3",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L3 cache in the different socket from the requests."
},
{
"ArchStdEvent": "L3D_CACHE_LMISS_RD",
"BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events."
"BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3 cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events. Note: This event may count inaccurately."
}
]

2
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ll_cache.json
View File

@@ -5,6 +5,6 @@
},
{
"ArchStdEvent": "LL_CACHE_MISS_RD",
"BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events."
"BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3 cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events. Note: This event may count inaccurately."
}
]

6
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/pipeline.json
View File

@@ -147,17 +147,17 @@
{
"EventCode": "0x02B0",
"EventName": "L1_PIPE_COMP_GATHER_2FLOW",
"BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined."
"BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 2-flows because 2 elements could not be combined."
},
{
"EventCode": "0x02B1",
"EventName": "L1_PIPE_COMP_GATHER_1FLOW",
"BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined."
"BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 1-flow because 2 elements could be combined."
},
{
"EventCode": "0x02B2",
"EventName": "L1_PIPE_COMP_GATHER_0FLOW",
"BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0."
"BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 0-flow because both predicate values are 0."
},
{
"EventCode": "0x02B3",

12
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/spec_operation.json
View File

@@ -81,7 +81,7 @@
},
{
"ArchStdEvent": "CSDB_SPEC",
"BriefDescription": "This event counts speculatively executed control speculation barrier instructions."
"BriefDescription": "This event counts architecturally executed control speculation barrier instructions."
},
{
"EventCode": "0x0108",
@@ -91,17 +91,17 @@
{
"EventCode": "0x0109",
"EventName": "IEL_SPEC",
"BriefDescription": "This event counts architecturally executed inter-element manipulation operations."
"BriefDescription": "This event counts architecturally executed inter-element manipulation operation."
},
{
"EventCode": "0x010A",
"EventName": "IREG_SPEC",
"BriefDescription": "This event counts architecturally executed inter-register manipulation operations."
"BriefDescription": "This event counts architecturally executed inter-register manipulation operation."
},
{
"EventCode": "0x011A",
"EventName": "BC_LD_SPEC",
"BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations."
"BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operation."
},
{
"EventCode": "0x011B",
@@ -130,7 +130,7 @@
},
{
"ArchStdEvent": "ASE_INST_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD operation."
},
{
"ArchStdEvent": "INT_SPEC",
@@ -158,7 +158,7 @@
},
{
"ArchStdEvent": "NONFP_SPEC",
"BriefDescription": "This event counts architecturally executed non-floating-point operations."
"BriefDescription": "This event counts architecturally executed non-floating-point operation."
},
{
"ArchStdEvent": "INT_SCALE_OPS_SPEC",

4
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/stall.json
View File

@@ -5,7 +5,7 @@
},
{
"ArchStdEvent": "STALL_BACKEND",
"BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because the backend is unable to accept any operations."
"BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because the backend is unable to accept any operation."
},
{
"ArchStdEvent": "STALL",
@@ -69,7 +69,7 @@
},
{
"ArchStdEvent": "STALL_BACKEND_L2D",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L2D cache."
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L2 cache."
},
{
"ArchStdEvent": "STALL_BACKEND_CPUBOUND",

44
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/sve.json
View File

@@ -13,11 +13,11 @@
},
{
"ArchStdEvent": "ASE_SVE_INST_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE operation."
},
{
"ArchStdEvent": "UOP_SPEC",
"BriefDescription": "This event counts all architecturally executed micro-operations."
"BriefDescription": "This event counts all architecturally executed micro-operation."
},
{
"ArchStdEvent": "SVE_MATH_SPEC",
@@ -29,7 +29,7 @@
},
{
"ArchStdEvent": "FP_FMA_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point fused multiply-add and multiply-subtract operations."
"BriefDescription": "This event counts architecturally executed floating-point fused multiply-add and multiply-subtract operation."
},
{
"ArchStdEvent": "FP_RECPE_SPEC",
@@ -41,15 +41,15 @@
},
{
"ArchStdEvent": "ASE_INT_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD integer operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD integer operation."
},
{
"ArchStdEvent": "SVE_INT_SPEC",
"BriefDescription": "This event counts architecturally executed SVE integer operations."
"BriefDescription": "This event counts architecturally executed SVE integer operation."
},
{
"ArchStdEvent": "ASE_SVE_INT_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE integer operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE integer operation."
},
{
"ArchStdEvent": "SVE_INT_DIV_SPEC",
@@ -69,7 +69,7 @@
},
{
"ArchStdEvent": "ASE_SVE_INT_MUL_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE integer multiply operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE integer multiply operation."
},
{
"ArchStdEvent": "SVE_INT_MUL64_SPEC",
@@ -77,19 +77,19 @@
},
{
"ArchStdEvent": "SVE_INT_MULH64_SPEC",
"BriefDescription": "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply returning high part operations."
"BriefDescription": "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply returning high part operation."
},
{
"ArchStdEvent": "ASE_NONFP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD non-floating-point operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD non-floating-point operation."
},
{
"ArchStdEvent": "SVE_NONFP_SPEC",
"BriefDescription": "This event counts architecturally executed SVE non-floating-point operations."
"BriefDescription": "This event counts architecturally executed SVE non-floating-point operation."
},
{
"ArchStdEvent": "ASE_SVE_NONFP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE non-floating-point operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE non-floating-point operation."
},
{
"ArchStdEvent": "ASE_INT_VREDUCE_SPEC",
@@ -101,7 +101,7 @@
},
{
"ArchStdEvent": "ASE_SVE_INT_VREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE integer reduction operations."
"BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE integer reduction operation."
},
{
"ArchStdEvent": "SVE_PERM_SPEC",
@@ -149,11 +149,11 @@
},
{
"ArchStdEvent": "ASE_SVE_LD_SPEC",
"BriefDescription": "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD load instructions."
"BriefDescription": "This event counts architecturally executed operations that read from memory due to Advanced SIMD or SVE load instructions."
},
{
"ArchStdEvent": "ASE_SVE_ST_SPEC",
"BriefDescription": "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD store instructions."
"BriefDescription": "This event counts architecturally executed operations that write to memory due to Advanced SIMD or SVE store instructions."
},
{
"ArchStdEvent": "PRF_SPEC",
@@ -197,11 +197,11 @@
},
{
"ArchStdEvent": "ASE_SVE_LD_MULTI_SPEC",
"BriefDescription": "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD multiple vector contiguous structure load instructions."
"BriefDescription": "This event counts architecturally executed operations that read from memory due to Advanced SIMD or SVE multiple vector contiguous structure load instructions."
},
{
"ArchStdEvent": "ASE_SVE_ST_MULTI_SPEC",
"BriefDescription": "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD multiple vector contiguous structure store instructions."
"BriefDescription": "This event counts architecturally executed operations that write to memory due to Advanced SIMD or SVE multiple vector contiguous structure store instructions."
},
{
"ArchStdEvent": "SVE_LD_GATHER_SPEC",
@@ -221,27 +221,27 @@
},
{
"ArchStdEvent": "FP_HP_SCALE_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed SVE half-precision arithmetic operations. See FP_HP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPEC."
"BriefDescription": "This event counts architecturally executed SVE half-precision arithmetic operation. See FP_HP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_HP_FIXED_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed v8SIMD&FP half-precision arithmetic operations. See FP_HP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 16-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
"BriefDescription": "This event counts architecturally executed v8SIMD&FP half-precision arithmetic operation. See FP_HP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 16-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_SP_SCALE_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed SVE single-precision arithmetic operations. See FP_SP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPEC."
"BriefDescription": "This event counts architecturally executed SVE single-precision arithmetic operation. See FP_SP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_SP_FIXED_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed v8SIMD&FP single-precision arithmetic operations. See FP_SP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 32-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
"BriefDescription": "This event counts architecturally executed v8SIMD&FP single-precision arithmetic operation. See FP_SP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 32-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_DP_SCALE_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed SVE double-precision arithmetic operations. See FP_DP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPEC."
"BriefDescription": "This event counts architecturally executed SVE double-precision arithmetic operation. See FP_DP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_DP_FIXED_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed v8SIMD&FP double-precision arithmetic operations. See FP_DP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2 for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
"BriefDescription": "This event counts architecturally executed v8SIMD&FP double-precision arithmetic operation. See FP_DP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2 for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
},
{
"ArchStdEvent": "ASE_SVE_INT_DOT_SPEC",

56
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/tlb.json
View File

@@ -104,72 +104,72 @@
{
"EventCode": "0x0C10",
"EventName": "L1I_TLB_REFILL_4K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 4KB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 4KB page."
},
{
"EventCode": "0x0C11",
"EventName": "L1I_TLB_REFILL_64K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 64KB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 64KB page."
},
{
"EventCode": "0x0C12",
"EventName": "L1I_TLB_REFILL_2M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 2MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 2MB page."
},
{
"EventCode": "0x0C13",
"EventName": "L1I_TLB_REFILL_32M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 32MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 32MB page."
},
{
"EventCode": "0x0C14",
"EventName": "L1I_TLB_REFILL_512M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 512MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 512MB page."
},
{
"EventCode": "0x0C15",
"EventName": "L1I_TLB_REFILL_1G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 1GB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 1GB page."
},
{
"EventCode": "0x0C16",
"EventName": "L1I_TLB_REFILL_16G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 16GB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 16GB page."
},
{
"EventCode": "0x0C18",
"EventName": "L1D_TLB_REFILL_4K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 4KB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1D in 4KB page."
},
{
"EventCode": "0x0C19",
"EventName": "L1D_TLB_REFILL_64K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 64KB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1D in 64KB page."
},
{
"EventCode": "0x0C1A",
"EventName": "L1D_TLB_REFILL_2M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 2MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1D in 2MB page."
},
{
"EventCode": "0x0C1B",
"EventName": "L1D_TLB_REFILL_32M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 32MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1D in 32MB page."
},
{
"EventCode": "0x0C1C",
"EventName": "L1D_TLB_REFILL_512M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 512MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1D in 512MB page."
},
{
"EventCode": "0x0C1D",
"EventName": "L1D_TLB_REFILL_1G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 1GB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1D in 1GB page."
},
{
"EventCode": "0x0C1E",
"EventName": "L1D_TLB_REFILL_16G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 16GB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L1D in 16GB page."
},
{
"EventCode": "0x0C20",
@@ -244,72 +244,72 @@
{
"EventCode": "0x0C30",
"EventName": "L2I_TLB_REFILL_4K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2Iin 4KB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2I in 4KB page."
},
{
"EventCode": "0x0C31",
"EventName": "L2I_TLB_REFILL_64K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 64KB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2I in 64KB page."
},
{
"EventCode": "0x0C32",
"EventName": "L2I_TLB_REFILL_2M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 2MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2I in 2MB page."
},
{
"EventCode": "0x0C33",
"EventName": "L2I_TLB_REFILL_32M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 32MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2I in 32MB page."
},
{
"EventCode": "0x0C34",
"EventName": "L2I_TLB_REFILL_512M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 512MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2I in 512MB page."
},
{
"EventCode": "0x0C35",
"EventName": "L2I_TLB_REFILL_1G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 1GB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2I in 1GB page."
},
{
"EventCode": "0x0C36",
"EventName": "L2I_TLB_REFILL_16G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 16GB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2I in 16GB page."
},
{
"EventCode": "0x0C38",
"EventName": "L2D_TLB_REFILL_4K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 4KB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2D in 4KB page."
},
{
"EventCode": "0x0C39",
"EventName": "L2D_TLB_REFILL_64K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 64KB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2D in 64KB page."
},
{
"EventCode": "0x0C3A",
"EventName": "L2D_TLB_REFILL_2M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 2MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2D in 2MB page."
},
{
"EventCode": "0x0C3B",
"EventName": "L2D_TLB_REFILL_32M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 32MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2D in 32MB page."
},
{
"EventCode": "0x0C3C",
"EventName": "L2D_TLB_REFILL_512M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 512MB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2D in 512MB page."
},
{
"EventCode": "0x0C3D",
"EventName": "L2D_TLB_REFILL_1G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 1GB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2D in 1GB page."
},
{
"EventCode": "0x0C3E",
"EventName": "L2D_TLB_REFILL_16G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 16GB page."
"BriefDescription": "This event counts operations that cause a TLB refill of the L2D in 16GB page."
},
{
"ArchStdEvent": "DTLB_WALK_PERCYC",

92
tools/perf/pmu-events/arch/common/common/software.json Normal file
View File

@@ -0,0 +1,92 @@
[
{
"Unit": "software",
"EventName": "cpu-clock",
"BriefDescription": "Per-CPU high-resolution timer based event",
"ConfigCode": "0"
},
{
"Unit": "software",
"EventName": "task-clock",
"BriefDescription": "Per-task high-resolution timer based event",
"ConfigCode": "1"
},
{
"Unit": "software",
"EventName": "faults",
"BriefDescription": "Number of page faults [This event is an alias of page-faults]",
"ConfigCode": "2"
},
{
"Unit": "software",
"EventName": "page-faults",
"BriefDescription": "Number of page faults [This event is an alias of faults]",
"ConfigCode": "2"
},
{
"Unit": "software",
"EventName": "context-switches",
"BriefDescription": "Number of context switches [This event is an alias of cs]",
"ConfigCode": "3"
},
{
"Unit": "software",
"EventName": "cs",
"BriefDescription": "Number of context switches [This event is an alias of context-switches]",
"ConfigCode": "3"
},
{
"Unit": "software",
"EventName": "cpu-migrations",
"BriefDescription": "Number of times a process has migrated to a new CPU [This event is an alias of migrations]",
"ConfigCode": "4"
},
{
"Unit": "software",
"EventName": "migrations",
"BriefDescription": "Number of times a process has migrated to a new CPU [This event is an alias of cpu-migrations]",
"ConfigCode": "4"
},
{
"Unit": "software",
"EventName": "minor-faults",
"BriefDescription": "Number of minor page faults. Minor faults don't require I/O to handle",
"ConfigCode": "5"
},
{
"Unit": "software",
"EventName": "major-faults",
"BriefDescription": "Number of major page faults. Major faults require I/O to handle",
"ConfigCode": "6"
},
{
"Unit": "software",
"EventName": "alignment-faults",
"BriefDescription": "Number of kernel handled memory alignment faults",
"ConfigCode": "7"
},
{
"Unit": "software",
"EventName": "emulation-faults",
"BriefDescription": "Number of kernel handled unimplemented instruction faults handled through emulation",
"ConfigCode": "8"
},
{
"Unit": "software",
"EventName": "dummy",
"BriefDescription": "A placeholder event that doesn't count anything",
"ConfigCode": "9"
},
{
"Unit": "software",
"EventName": "bpf-output",
"BriefDescription": "An event used by BPF programs to write to the perf ring buffer",
"ConfigCode": "10"
},
{
"Unit": "software",
"EventName": "cgroup-switches",
"BriefDescription": "Number of context switches to a task in a different cgroup",
"ConfigCode": "11"
}
]

14
tools/perf/pmu-events/arch/s390/cf_z16/pai_crypto.json
View File

@@ -753,14 +753,14 @@
"EventCode": "4203",
"EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_TDEA_128",
"BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED TDEA 128",
"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-TDEA- 128 function ending with CC=0"
"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-TDEA-128 function ending with CC=0"
},
{
"Unit": "PAI-CRYPTO",
"EventCode": "4204",
"EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_TDEA_192",
"BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED TDEA 192",
"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-TDEA- 192 function ending with CC=0"
"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-TDEA-192 function ending with CC=0"
},
{
"Unit": "PAI-CRYPTO",
@@ -788,21 +788,21 @@
"EventCode": "4208",
"EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_AES_128",
"BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED AES 128",
"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-AES- 128 function ending with CC=0"
"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-AES-128 function ending with CC=0"
},
{
"Unit": "PAI-CRYPTO",
"EventCode": "4209",
"EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_AES_192",
"BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED AES 192",
"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-AES- 192 function ending with CC=0"
"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-AES-192 function ending with CC=0"
},
{
"Unit": "PAI-CRYPTO",
"EventCode": "4210",
"EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_AES_256A",
"BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED AES 256A",
"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-AES- 256A function ending with CC=0"
"EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_AES_256",
"BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED AES 256",
"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-AES-256 function ending with CC=0"
},
{
"Unit": "PAI-CRYPTO",

58
tools/perf/pmu-events/arch/s390/cf_z17/basic.json Normal file
View File

@@ -0,0 +1,58 @@
[
{
"Unit": "CPU-M-CF",
"EventCode": "0",
"EventName": "CPU_CYCLES",
"BriefDescription": "Cycle Count",
"PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state."
},
{
"Unit": "CPU-M-CF",
"EventCode": "1",
"EventName": "INSTRUCTIONS",
"BriefDescription": "Instruction Count",
"PublicDescription": "This counter counts the total number of instructions executed by the CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "2",
"EventName": "L1I_DIR_WRITES",
"BriefDescription": "Level-1 I-Cache Directory Write Count",
"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes."
},
{
"Unit": "CPU-M-CF",
"EventCode": "3",
"EventName": "L1I_PENALTY_CYCLES",
"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "4",
"EventName": "L1D_DIR_WRITES",
"BriefDescription": "Level-1 D-Cache Directory Write Count",
"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes."
},
{
"Unit": "CPU-M-CF",
"EventCode": "5",
"EventName": "L1D_PENALTY_CYCLES",
"BriefDescription": "Level-1 D-Cache Penalty Cycle Count",
"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "32",
"EventName": "PROBLEM_STATE_CPU_CYCLES",
"BriefDescription": "Problem-State Cycle Count",
"PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state."
},
{
"Unit": "CPU-M-CF",
"EventCode": "33",
"EventName": "PROBLEM_STATE_INSTRUCTIONS",
"BriefDescription": "Problem-State Instruction Count",
"PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state."
}
]

142
tools/perf/pmu-events/arch/s390/cf_z17/crypto6.json Normal file
View File

@@ -0,0 +1,142 @@
[
{
"Unit": "CPU-M-CF",
"EventCode": "64",
"EventName": "PRNG_FUNCTIONS",
"BriefDescription": "PRNG Function Count",
"PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "65",
"EventName": "PRNG_CYCLES",
"BriefDescription": "PRNG Cycle Count",
"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "66",
"EventName": "PRNG_BLOCKED_FUNCTIONS",
"BriefDescription": "PRNG Blocked Function Count",
"PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "67",
"EventName": "PRNG_BLOCKED_CYCLES",
"BriefDescription": "PRNG Blocked Cycle Count",
"PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "68",
"EventName": "SHA_FUNCTIONS",
"BriefDescription": "SHA Function Count",
"PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "69",
"EventName": "SHA_CYCLES",
"BriefDescription": "SHA Cycle Count",
"PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "70",
"EventName": "SHA_BLOCKED_FUNCTIONS",
"BriefDescription": "SHA Blocked Function Count",
"PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "71",
"EventName": "SHA_BLOCKED_CYCLES",
"BriefDescription": "SHA Blocked Cycle Count",
"PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "72",
"EventName": "DEA_FUNCTIONS",
"BriefDescription": "DEA Function Count",
"PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "73",
"EventName": "DEA_CYCLES",
"BriefDescription": "DEA Cycle Count",
"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "74",
"EventName": "DEA_BLOCKED_FUNCTIONS",
"BriefDescription": "DEA Blocked Function Count",
"PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "75",
"EventName": "DEA_BLOCKED_CYCLES",
"BriefDescription": "DEA Blocked Cycle Count",
"PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "76",
"EventName": "AES_FUNCTIONS",
"BriefDescription": "AES Function Count",
"PublicDescription": "This counter counts the total number of the AES functions issued by the CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "77",
"EventName": "AES_CYCLES",
"BriefDescription": "AES Cycle Count",
"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "78",
"EventName": "AES_BLOCKED_FUNCTIONS",
"BriefDescription": "AES Blocked Function Count",
"PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "79",
"EventName": "AES_BLOCKED_CYCLES",
"BriefDescription": "AES Blocked Cycle Count",
"PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "80",
"EventName": "ECC_FUNCTION_COUNT",
"BriefDescription": "ECC Function Count",
"PublicDescription": "This counter counts the total number of the elliptic-curve cryptography (ECC) functions issued by the CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "81",
"EventName": "ECC_CYCLES_COUNT",
"BriefDescription": "ECC Cycles Count",
"PublicDescription": "This counter counts the total number of CPU cycles when the ECC coprocessor is busy performing the elliptic-curve cryptography (ECC) functions issued by the CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "82",
"EventName": "ECC_BLOCKED_FUNCTION_COUNT",
"BriefDescription": "Ecc Blocked Function Count",
"PublicDescription": "This counter counts the total number of the elliptic-curve cryptography (ECC) functions that are issued by the CPU and are blocked because the ECC coprocessor is busy performing a function issued by another CPU."
},
{
"Unit": "CPU-M-CF",
"EventCode": "83",
"EventName": "ECC_BLOCKED_CYCLES_COUNT",
"BriefDescription": "ECC Blocked Cycles Count",
"PublicDescription": "This counter counts the total number of CPU cycles blocked for the elliptic-curve cryptography (ECC) functions issued by the CPU because the ECC coprocessor is busy performing a function issued by another CPU."
}
]

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[
{
"Unit": "CPU-M-CF",
"EventCode": "128",
"EventName": "L1D_RO_EXCL_WRITES",
"BriefDescription": "L1D Read-only Exclusive Writes",
"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
},
{
"Unit": "CPU-M-CF",
"EventCode": "129",
"EventName": "DTLB2_WRITES",
"BriefDescription": "DTLB2 Writes",
"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines."
},
{
"Unit": "CPU-M-CF",
"EventCode": "130",
"EventName": "DTLB2_MISSES",
"BriefDescription": "DTLB2 Misses",
"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines."
},
{
"Unit": "CPU-M-CF",
"EventCode": "131",
"EventName": "CRSTE_1MB_WRITES",
"BriefDescription": "One Megabyte CRSTE writes",
"PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page."
},
{
"Unit": "CPU-M-CF",
"EventCode": "132",
"EventName": "DTLB2_GPAGE_WRITES",
"BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB."
},
{
"Unit": "CPU-M-CF",
"EventCode": "134",
"EventName": "ITLB2_WRITES",
"BriefDescription": "ITLB2 Writes",
"PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines."
},
{
"Unit": "CPU-M-CF",
"EventCode": "135",
"EventName": "ITLB2_MISSES",
"BriefDescription": "ITLB2 Misses",
"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines."
},
{
"Unit": "CPU-M-CF",
"EventCode": "137",
"EventName": "TLB2_PTE_WRITES",
"BriefDescription": "TLB2 Page Table Entry Writes",
"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
},
{
"Unit": "CPU-M-CF",
"EventCode": "138",
"EventName": "TLB2_CRSTE_WRITES",
"BriefDescription": "TLB2 Combined Region and Segment Entry Writes",
"PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
},
{
"Unit": "CPU-M-CF",
"EventCode": "139",
"EventName": "TLB2_ENGINES_BUSY",
"BriefDescription": "TLB2 Engines Busy",
"PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
},
{
"Unit": "CPU-M-CF",
"EventCode": "140",
"EventName": "TX_C_TEND",
"BriefDescription": "Completed TEND instructions in constrained TX mode",
"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
},
{
"Unit": "CPU-M-CF",
"EventCode": "141",
"EventName": "TX_NC_TEND",
"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode."
},
{
"Unit": "CPU-M-CF",
"EventCode": "143",
"EventName": "L1C_TLB2_MISSES",
"BriefDescription": "L1C TLB2 Misses",
"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-2 TLB miss is in progress."
},
{
"Unit": "CPU-M-CF",
"EventCode": "145",
"EventName": "DCW_REQ",
"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache",
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "146",
"EventName": "DCW_REQ_IV",
"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Intervention",
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
},
{
"Unit": "CPU-M-CF",
"EventCode": "147",
"EventName": "DCW_REQ_CHIP_HIT",
"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Chip HP Hit",
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "148",
"EventName": "DCW_REQ_DRAWER_HIT",
"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Drawer HP Hit",
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "149",
"EventName": "DCW_ON_CHIP",
"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache",
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "150",
"EventName": "DCW_ON_CHIP_IV",
"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Intervention",
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention."
},
{
"Unit": "CPU-M-CF",
"EventCode": "151",
"EventName": "DCW_ON_CHIP_CHIP_HIT",
"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Chip HP Hit",
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "152",
"EventName": "DCW_ON_CHIP_DRAWER_HIT",
"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Drawer HP Hit",
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "153",
"EventName": "DCW_ON_MODULE",
"BriefDescription": "Directory Write Level 1 Data Cache from On-Module L2-Cache",
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "154",
"EventName": "DCW_ON_DRAWER",
"BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer L2-Cache",
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "155",
"EventName": "DCW_OFF_DRAWER",
"BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer L2-Cache",
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "156",
"EventName": "DCW_ON_CHIP_MEMORY",
"BriefDescription": "Directory Write Level 1 Cache from On-Chip Memory",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory."
},
{
"Unit": "CPU-M-CF",
"EventCode": "157",
"EventName": "DCW_ON_MODULE_MEMORY",
"BriefDescription": "Directory Write Level 1 Cache from On-Module Memory",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory."
},
{
"Unit": "CPU-M-CF",
"EventCode": "158",
"EventName": "DCW_ON_DRAWER_MEMORY",
"BriefDescription": "Directory Write Level 1 Cache from On-Drawer Memory",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory."
},
{
"Unit": "CPU-M-CF",
"EventCode": "159",
"EventName": "DCW_OFF_DRAWER_MEMORY",
"BriefDescription": "Directory Write Level 1 Cache from Off-Drawer Memory",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory."
},
{
"Unit": "CPU-M-CF",
"EventCode": "160",
"EventName": "IDCW_ON_MODULE_IV",
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Intervention",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention."
},
{
"Unit": "CPU-M-CF",
"EventCode": "161",
"EventName": "IDCW_ON_MODULE_CHIP_HIT",
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Chip Hit",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "162",
"EventName": "IDCW_ON_MODULE_DRAWER_HIT",
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Drawer Hit",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "163",
"EventName": "IDCW_ON_DRAWER_IV",
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Intervention",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention."
},
{
"Unit": "CPU-M-CF",
"EventCode": "164",
"EventName": "IDCW_ON_DRAWER_CHIP_HIT",
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Chip Hit",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "165",
"EventName": "IDCW_ON_DRAWER_DRAWER_HIT",
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Drawer Hit",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "166",
"EventName": "IDCW_OFF_DRAWER_IV",
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Intervention",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention."
},
{
"Unit": "CPU-M-CF",
"EventCode": "167",
"EventName": "IDCW_OFF_DRAWER_CHIP_HIT",
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Chip Hit",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "168",
"EventName": "IDCW_OFF_DRAWER_DRAWER_HIT",
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Drawer Hit",
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "169",
"EventName": "ICW_REQ",
"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache",
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "170",
"EventName": "ICW_REQ_IV",
"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Intervention",
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
},
{
"Unit": "CPU-M-CF",
"EventCode": "171",
"EventName": "ICW_REQ_CHIP_HIT",
"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Chip HP Hit",
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "172",
"EventName": "ICW_REQ_DRAWER_HIT",
"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Drawer HP Hit",
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "173",
"EventName": "ICW_ON_CHIP",
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache",
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "174",
"EventName": "ICW_ON_CHIP_IV",
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Intervention",
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention."
},
{
"Unit": "CPU-M-CF",
"EventCode": "175",
"EventName": "ICW_ON_CHIP_CHIP_HIT",
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Chip HP Hit",
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "176",
"EventName": "ICW_ON_CHIP_DRAWER_HIT",
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Drawer HP Hit",
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache after using drawer level horizontal persistence, Drawer-HP hit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "177",
"EventName": "ICW_ON_MODULE",
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module L2-Cache",
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "178",
"EventName": "ICW_ON_DRAWER",
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer L2-Cache",
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "179",
"EventName": "ICW_OFF_DRAWER",
"BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer L2-Cache",
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache."
},
{
"Unit": "CPU-M-CF",
"EventCode": "202",
"EventName": "CYCLES_SAMETHRD",
"BriefDescription": "CPU is not in wait state and CPU is running by itself",
"PublicDescription": "The number of cycles the CPU is not in wait state and the CPU is running by itself on the Core."
},
{
"Unit": "CPU-M-CF",
"EventCode": "203",
"EventName": "CYCLES_DIFFTHRD",
"BriefDescription": "CPU is not in wait state and CPU is running by another thread",
"PublicDescription": "The number of cycles the CPU is not in wait state and the CPU is running with another thread on the Core."
},
{
"Unit": "CPU-M-CF",
"EventCode": "204",
"EventName": "INST_SAMETHRD",
"BriefDescription": "Instructions executed on CPU by itself",
"PublicDescription": "The number of instructions executed on the CPU and the CPU is running by itself on the Core."
},
{
"Unit": "CPU-M-CF",
"EventCode": "205",
"EventName": "INST_DIFFTHRD",
"BriefDescription": "Instructions executed on CPU by another thread",
"PublicDescription": "The number of instructions executed on the CPU and the CPU is running with another thread on the Core."
},
{
"Unit": "CPU-M-CF",
"EventCode": "206",
"EventName": "WRONG_BRANCH_PREDICTION",
"BriefDescription": "Incorrect branch prediction on core",
"PublicDescription": "A count of the number of branches that were predicted incorrectly by the branch prediction logic in the Core. This includes incorrectly predicted branches that are executed in Firmware. Examples of instructions implemented in Firmware are complicated instructions like MVCL (Move Character Long) and PC (Program Call)."
},
{
"Unit": "CPU-M-CF",
"EventCode": "225",
"EventName": "VX_BCD_EXECUTION_SLOTS",
"BriefDescription": "Count finished vector arithmetic Binary Coded Decimal instructions",
"PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMP, VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, VCVDG, VSCHP, VSCSHP, VCSPH, VCLZDP, VPKZR, VSRPR, VUPKZH, VUPKZL, VTZ, VUPH, VUPL, VCVBX, VCVDX."
},
{
"Unit": "CPU-M-CF",
"EventCode": "226",
"EventName": "DECIMAL_INSTRUCTIONS",
"BriefDescription": "Decimal instruction dispatched",
"PublicDescription": "Decimal instruction dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP, TP."
},
{
"Unit": "CPU-M-CF",
"EventCode": "232",
"EventName": "LAST_HOST_TRANSLATIONS",
"BriefDescription": "Last host translation done",
"PublicDescription": "Last Host Translation done."
},
{
"Unit": "CPU-M-CF",
"EventCode": "244",
"EventName": "TX_NC_TABORT",
"BriefDescription": "Aborted transactions in unconstrained TX mode",
"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode."
},
{
"Unit": "CPU-M-CF",
"EventCode": "245",
"EventName": "TX_C_TABORT_NO_SPECIAL",
"BriefDescription": "Aborted transactions in constrained TX mode",
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
},
{
"Unit": "CPU-M-CF",
"EventCode": "246",
"EventName": "TX_C_TABORT_SPECIAL",
"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
},
{
"Unit": "CPU-M-CF",
"EventCode": "248",
"EventName": "DFLT_ACCESS",
"BriefDescription": "Cycles CPU spent obtaining access to Deflate unit",
"PublicDescription": "Cycles CPU spent obtaining access to Deflate unit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "253",
"EventName": "DFLT_CYCLES",
"BriefDescription": "Cycles CPU is using Deflate unit",
"PublicDescription": "Cycles CPU is using Deflate unit."
},
{
"Unit": "CPU-M-CF",
"EventCode": "256",
"EventName": "SORTL",
"BriefDescription": "Count SORTL instructions",
"PublicDescription": "Increments by one for every SORT LISTS (SORTL) instruction executed."
},
{
"Unit": "CPU-M-CF",
"EventCode": "265",
"EventName": "DFLT_CC",
"BriefDescription": "Increments DEFLATE CONVERSION CALL",
"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL (DFLTCC) instruction executed."
},
{
"Unit": "CPU-M-CF",
"EventCode": "266",
"EventName": "DFLT_CCFINISH",
"BriefDescription": "Increments completed DEFLATE CONVERSION CALL",
"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL (DFLTCC) instruction executed that ended in Condition Codes 0, 1 or 2."
},
{
"Unit": "CPU-M-CF",
"EventCode": "267",
"EventName": "NNPA_INVOCATIONS",
"BriefDescription": "NNPA Total invocations",
"PublicDescription": "Increments by one for every NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction executed."
},
{
"Unit": "CPU-M-CF",
"EventCode": "268",
"EventName": "NNPA_COMPLETIONS",
"BriefDescription": "NNPA Total completions",
"PublicDescription": "Increments by one for every NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction executed that ended in Condition Code 0."
},
{
"Unit": "CPU-M-CF",
"EventCode": "269",
"EventName": "NNPA_WAIT_LOCK",
"BriefDescription": "Cycles spent obtaining NNPA lock",
"PublicDescription": "Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI."
},
{
"Unit": "CPU-M-CF",
"EventCode": "270",
"EventName": "NNPA_HOLD_LOCK",
"BriefDescription": "Cycles spent holding NNPA lock",
"PublicDescription": "Cycles CPU is using IBM Z Integrated Accelerator for AI."
},
{
"Unit": "CPU-M-CF",
"EventCode": "272",
"EventName": "NNPA_INST_ONCHIP",
"BriefDescription": "NNPA instructions used on-chip Integrated Accelerator",
"PublicDescription": "A NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction has used the Local On-Chip IBM Z Integrated Accelerator for AI during its execution"
},
{
"Unit": "CPU-M-CF",
"EventCode": "273",
"EventName": "NNPA_INST_OFFCHIP",
"BriefDescription": "NNPA instructions used off-chip Integrated Accelerator",
"PublicDescription": "A NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction has used an Off-Chip IBM Z Integrated Accelerator for AI during its execution."
},
{
"Unit": "CPU-M-CF",
"EventCode": "274",
"EventName": "NNPA_INST_DIFF",
"BriefDescription": "NNPA instructions used different Integrated Accelerator",
"PublicDescription": "A NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction has used a different IBM Z Integrated Accelerator for AI since it was last executed."
},
{
"Unit": "CPU-M-CF",
"EventCode": "276",
"EventName": "NNPA_4K_PREFETCH",
"BriefDescription": "Number of 4K prefetches for Integated Accelerator",
"PublicDescription": "Number of 4K prefetches done for a remote IBM Z Integated Accelerator for AI."
},
{
"Unit": "CPU-M-CF",
"EventCode": "277",
"EventName": "NNPA_COMPL_LOCK",
"BriefDescription": "A Perform Locked Operation has completed",
"PublicDescription": "A PERFORM LOCKED OPERATION (PLO) has completed."
},
{
"Unit": "CPU-M-CF",
"EventCode": "278",
"EventName": "NNPA_RETRY_LOCK",
"BriefDescription": "A Perform Locked Operation has been retried",
"PublicDescription": "A PERFORM LOCKED OPERATION (PLO) has been retried and the CPU did not use any special logic to allow the PLO to complete."
},
{
"Unit": "CPU-M-CF",
"EventCode": "279",
"EventName": "NNPA_RETRY_LOCK_WITH_PLO",
"BriefDescription": "A Perform Locked Operation has been retried using special logic",
"PublicDescription": "A PERFORM LOCKED OPERATION (PLO) has been retried and the CPU is using special logic to allow PLO to complete."
},
{
"Unit": "CPU-M-CF",
"EventCode": "448",
"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
"BriefDescription": "Cycle count with one thread active",
"PublicDescription": "Cycle count with one thread active"
},
{
"Unit": "CPU-M-CF",
"EventCode": "449",
"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
"BriefDescription": "Cycle count with two threads active",
"PublicDescription": "Cycle count with two threads active"
}
]

1213
tools/perf/pmu-events/arch/s390/cf_z17/pai_crypto.json Normal file
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261
tools/perf/pmu-events/arch/s390/cf_z17/pai_ext.json Normal file
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@@ -0,0 +1,261 @@
[
{
"Unit": "PAI-EXT",
"EventCode": "6144",
"EventName": "NNPA_ALL",
"BriefDescription": "NNPA ALL",
"PublicDescription": "Sums of all non zero NNPA counters"
},
{
"Unit": "PAI-EXT",
"EventCode": "6145",
"EventName": "NNPA_ADD",
"BriefDescription": "NNPA ADD function",
"PublicDescription": "NNPA-ADD function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6146",
"EventName": "NNPA_SUB",
"BriefDescription": "NNPA SUB function",
"PublicDescription": "NNPA-SUB function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6147",
"EventName": "NNPA_MUL",
"BriefDescription": "NNPA MUL function",
"PublicDescription": "NNPA-MUL function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6148",
"EventName": "NNPA_DIV",
"BriefDescription": "NNPA_DIV function",
"PublicDescription": "NNPA-DIV function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6149",
"EventName": "NNPA_MIN",
"BriefDescription": "NNPA MIN function",
"PublicDescription": "NNPA-MIN function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6150",
"EventName": "NNPA_MAX",
"BriefDescription": "NNPA MAX function",
"PublicDescription": "NNPA-MAX function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6151",
"EventName": "NNPA_LOG",
"BriefDescription": "NNPA LOG function",
"PublicDescription": "NNPA Log function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6152",
"EventName": "NNPA_EXP",
"BriefDescription": "NNPA EXP function",
"PublicDescription": "NNPA-EXP function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6153",
"EventName": "NNPA_IBM_RESERVED_9",
"BriefDescription": "Reserved for IBM use",
"PublicDescription": "Reserved for IBM use"
},
{
"Unit": "PAI-EXT",
"EventCode": "6154",
"EventName": "NNPA_RELU",
"BriefDescription": "NNPA RELU function",
"PublicDescription": "NNPA-RELU function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6155",
"EventName": "NNPA_TANH",
"BriefDescription": "NNPA TANH function",
"PublicDescription": "NNPA-TANH function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6156",
"EventName": "NNPA_SIGMOID",
"BriefDescription": "NNPA SIGMOID function",
"PublicDescription": "NNPA-SIGMOID function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6157",
"EventName": "NNPA_SOFTMAX",
"BriefDescription": "NNPA SOFTMAX function",
"PublicDescription": "NNPA-SOFTMAX function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6158",
"EventName": "NNPA_BATCHNORM",
"BriefDescription": "NNPA BATCHNORM function",
"PublicDescription": "NNPA-BATCHNORM function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6159",
"EventName": "NNPA_MAXPOOL2D",
"BriefDescription": "NNPA MAXPOOL2D function",
"PublicDescription": "NNPA-MAXPOOL2D function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6160",
"EventName": "NNPA_AVGPOOL2D",
"BriefDescription": "NNPA_AVGPOOL2D function",
"PublicDescription": "NNPA-AVGPOOL2D function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6161",
"EventName": "NNPA_LSTMACT",
"BriefDescription": "NNPA LSTMACT function",
"PublicDescription": "NNPA-LSTMACT function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6162",
"EventName": "NNPA_GRUACT",
"BriefDescription": "NNPA GRUACT function",
"PublicDescription": "NNPA-GRUACT function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6163",
"EventName": "NNPA_CONVOLUTION",
"BriefDescription": "NNPA CONVOLUTION function",
"PublicDescription": "NNPA-CONVOLUTION function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6164",
"EventName": "NNPA_MATMUL_OP",
"BriefDescription": "NNPA MATMUL OP function",
"PublicDescription": "NNPA-MATMUL-OP function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6165",
"EventName": "NNPA_MATMUL_OP_BCAST23",
"BriefDescription": "NNPA MATMUL OP BCAST23 function",
"PublicDescription": "NNPA-MATMUL-OP-BCAST23 function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6166",
"EventName": "NNPA_SMALLBATCH",
"BriefDescription": "NNPA Counter 22",
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
},
{
"Unit": "PAI-EXT",
"EventCode": "6167",
"EventName": "NNPA_LARGEDIM",
"BriefDescription": "NNPA Counter 23",
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
},
{
"Unit": "PAI-EXT",
"EventCode": "6168",
"EventName": "NNPA_SMALLTENSOR",
"BriefDescription": "NNPA Counter 24",
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
},
{
"Unit": "PAI-EXT",
"EventCode": "6169",
"EventName": "NNPA_1MFRAME",
"BriefDescription": "NNPA Counter 25",
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
},
{
"Unit": "PAI-EXT",
"EventCode": "6170",
"EventName": "NNPA_2GFRAME",
"BriefDescription": "NNPA Counter 26",
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
},
{
"Unit": "PAI-EXT",
"EventCode": "6171",
"EventName": "NNPA_ACCESSEXCEPT",
"BriefDescription": "NNPA Counter 27",
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
},
{
"Unit": "PAI-EXT",
"EventCode": "6172",
"EventName": "NNPA_TRANSFORM",
"BriefDescription": "NNPA-TRANSFORM function",
"PublicDescription": "NNPA-TRANSFORM function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6173",
"EventName": "NNPA_GELU",
"BriefDescription": "NNPA-GELU function",
"PublicDescription": "NNPA-GELU function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6174",
"EventName": "NNPA_MOMENTS",
"BriefDescription": "NNPA-MOMENTS function",
"PublicDescription": "NNPA-MOMENTS function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6175",
"EventName": "NNPA_LAYERNORM",
"BriefDescription": "NNPA-LAYERNORM function",
"PublicDescription": "NNPA-LAYERNORM function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6176",
"EventName": "NNPA_MATMUL_OP_BCAST1",
"BriefDescription": "NNPA-MATMUL_OP_BCAST1 function",
"PublicDescription": "NNPA-MATMUL-OP-BCAST1 function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6177",
"EventName": "NNPA_SQRT",
"BriefDescription": "NNPA-SQRT function",
"PublicDescription": "NNPA-SQRT function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6178",
"EventName": "NNPA_INVSQRT",
"BriefDescription": "NNPA-INVSQRT function",
"PublicDescription": "NNPA-INVSQRT function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6179",
"EventName": "NNPA_NORM",
"BriefDescription": "NNPA-NORM function",
"PublicDescription": "NNPA-NORM function ending with CC=0"
},
{
"Unit": "PAI-EXT",
"EventCode": "6180",
"EventName": "NNPA_REDUCE",
"BriefDescription": "NNPA-REDUCE function",
"PublicDescription": "NNPA-REDUCE function ending with CC=0"
}
]

72
tools/perf/pmu-events/arch/s390/cf_z17/transaction.json Normal file
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@@ -0,0 +1,72 @@
[
{
"BriefDescription": "Transaction count",
"MetricName": "transaction",
"MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL if has_event(TX_C_TEND) else 0"
},
{
"BriefDescription": "Cycles per Instruction",
"MetricName": "cpi",
"MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) else 0"
},
{
"BriefDescription": "Problem State Instruction Ratio",
"MetricName": "prbstate",
"MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0"
},
{
"BriefDescription": "Level One Miss per 100 Instructions",
"MetricName": "l1mp",
"MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0"
},
{
"BriefDescription": "Percentage sourced from Level 2 cache",
"MetricName": "l2p",
"MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ) else 0"
},
{
"BriefDescription": "Percentage sourced from Level 3 on same chip cache",
"MetricName": "l3p",
"MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_CHIP_HIT) else 0"
},
{
"BriefDescription": "Percentage sourced from Level 4 Local cache on same drawer",
"MetricName": "l4lp",
"MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_DRAWER_HIT) else 0"
},
{
"BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
"MetricName": "l4rp",
"MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_OFF_DRAWER) else 0"
},
{
"BriefDescription": "Percentage sourced from memory",
"MetricName": "memp",
"MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_ON_CHIP_MEMORY) else 0"
},
{
"BriefDescription": "Cycles per Instructions from Finite cache/memory",
"MetricName": "finite_cpi",
"MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS if has_event(L1C_TLB2_MISSES) else 0"
},
{
"BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
"MetricName": "est_cpi",
"MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0"
},
{
"BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
"MetricName": "scpl1m",
"MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES) if has_event(L1C_TLB2_MISSES) else 0"
},
{
"BriefDescription": "Estimated TLB CPU percentage of Total CPU",
"MetricName": "tlb_percent",
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100 if has_event(CPU_CYCLES) else 0"
},
{
"BriefDescription": "Estimated Cycles per TLB Miss",
"MetricName": "tlb_miss",
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) if has_event(DTLB2_MISSES) else 0"
}
]

1
tools/perf/pmu-events/arch/s390/mapfile.csv
View File

@@ -6,3 +6,4 @@ Family-model,Version,Filename,EventType
^IBM.390[67].*[13]\.[1-5].[[:xdigit:]]+$,3,cf_z14,core
^IBM.856[12].*3\.6.[[:xdigit:]]+$,3,cf_z15,core
^IBM.393[12].*$,3,cf_z16,core
^IBM.917[56].*$,3,cf_z17,core
1 Family-model Version Filename EventType
6 ^IBM.390[67].*[13]\.[1-5].[[:xdigit:]]+$ 3 cf_z14 core
7 ^IBM.856[12].*3\.6.[[:xdigit:]]+$ 3 cf_z15 core
8 ^IBM.393[12].*$ 3 cf_z16 core
9 ^IBM.917[56].*$ 3 cf_z17 core

56
tools/perf/pmu-events/arch/x86/alderlake/cache.json
View File

@@ -728,7 +728,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
"PublicDescription": "Counts the number of load uops retired that hit in DRAM. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x80",
"Unit": "cpu_atom"
@@ -739,7 +738,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
"PublicDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x20",
"Unit": "cpu_atom"
@@ -750,7 +748,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PublicDescription": "Counts the number of load uops retired that hit in the L1 data cache. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x1",
"Unit": "cpu_atom"
@@ -761,7 +758,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"PublicDescription": "Counts the number of load uops retired that miss in the L1 data cache. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x8",
"Unit": "cpu_atom"
@@ -772,7 +768,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PublicDescription": "Counts the number of load uops retired that hit in the L2 cache. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x2",
"Unit": "cpu_atom"
@@ -783,7 +778,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PublicDescription": "Counts the number of load uops retired that miss in the L2 cache. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x10",
"Unit": "cpu_atom"
@@ -794,7 +788,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"PublicDescription": "Counts the number of load uops retired that hit in the L3 cache. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x4",
"Unit": "cpu_atom"
@@ -805,7 +798,6 @@
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_UOPS_RETIRED_MISC.HIT_E_F",
"PublicDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required, and non-modified data was forwarded. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x40",
"Unit": "cpu_atom"
@@ -816,7 +808,6 @@
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_UOPS_RETIRED_MISC.L3_MISS",
"PublicDescription": "Counts the number of load uops retired that miss in the L3 cache. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x20",
"Unit": "cpu_atom"
@@ -873,7 +864,7 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PublicDescription": "Counts the total number of load uops retired. Available PDIST counters: 0",
"PublicDescription": "Counts the total number of load uops retired.",
"SampleAfterValue": "200003",
"UMask": "0x81",
"Unit": "cpu_atom"
@@ -884,111 +875,111 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PublicDescription": "Counts the total number of store uops retired. Available PDIST counters: 0",
"PublicDescription": "Counts the total number of store uops retired.",
"SampleAfterValue": "200003",
"UMask": "0x82",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
@@ -999,7 +990,6 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PublicDescription": "Counts the number of load uops retired that performed one or more locks. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x21",
"Unit": "cpu_atom"
@@ -1010,7 +1000,6 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PublicDescription": "Counts the number of retired split load uops. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x41",
"Unit": "cpu_atom"
@@ -1021,7 +1010,6 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS",
"PublicDescription": "Counts the total number of load and store uops retired that missed in the second level TLB. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x13",
"Unit": "cpu_atom"
@@ -1032,7 +1020,6 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
"PublicDescription": "Counts the number of load ops retired that miss in the second Level TLB. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x11",
"Unit": "cpu_atom"
@@ -1043,7 +1030,6 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"PublicDescription": "Counts the number of store ops retired that miss in the second level TLB. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x12",
"Unit": "cpu_atom"
@@ -1054,7 +1040,7 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
"PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x6",
"Unit": "cpu_atom"
@@ -1478,12 +1464,12 @@
"Unit": "cpu_core"
},
{
"BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.",
"BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
"PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO Available PDIST counters: 0",
"PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_core"

1
tools/perf/pmu-events/arch/x86/alderlake/floating-point.json
View File

@@ -213,7 +213,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.FPDIV",
"PublicDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt). Available PDIST counters: 0",
"SampleAfterValue": "2000003",
"UMask": "0x8",
"Unit": "cpu_atom"

1
tools/perf/pmu-events/arch/x86/alderlake/other.json
View File

@@ -55,7 +55,6 @@
"Deprecated": "1",
"EventCode": "0xe4",
"EventName": "LBR_INSERTS.ANY",
"PublicDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS] Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_atom"

44
tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
View File

@@ -128,7 +128,7 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for. Available PDIST counters: 0",
"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
"SampleAfterValue": "200003",
"Unit": "cpu_atom"
},
@@ -147,7 +147,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.CALL",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xf9",
"Unit": "cpu_atom"
@@ -157,7 +156,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PublicDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x7e",
"Unit": "cpu_atom"
@@ -187,7 +185,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PublicDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfe",
"Unit": "cpu_atom"
@@ -207,7 +204,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PublicDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xbf",
"Unit": "cpu_atom"
@@ -227,7 +223,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PublicDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xeb",
"Unit": "cpu_atom"
@@ -247,7 +242,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT_CALL",
"PublicDescription": "Counts the number of near indirect CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfb",
"Unit": "cpu_atom"
@@ -258,7 +252,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfb",
"Unit": "cpu_atom"
@@ -269,7 +262,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.JCC",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x7e",
"Unit": "cpu_atom"
@@ -279,7 +271,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PublicDescription": "Counts the number of near CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xf9",
"Unit": "cpu_atom"
@@ -299,7 +290,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PublicDescription": "Counts the number of near RET branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xf7",
"Unit": "cpu_atom"
@@ -319,7 +309,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PublicDescription": "Counts the number of near taken branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xc0",
"Unit": "cpu_atom"
@@ -340,7 +329,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xeb",
"Unit": "cpu_atom"
@@ -350,7 +338,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PublicDescription": "Counts the number of near relative CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfd",
"Unit": "cpu_atom"
@@ -361,7 +348,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.RETURN",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xf7",
"Unit": "cpu_atom"
@@ -372,7 +358,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfe",
"Unit": "cpu_atom"
@@ -382,7 +367,7 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. Available PDIST counters: 0",
"PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
"SampleAfterValue": "200003",
"Unit": "cpu_atom"
},
@@ -400,7 +385,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PublicDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x7e",
"Unit": "cpu_atom"
@@ -430,7 +414,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
"PublicDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfe",
"Unit": "cpu_atom"
@@ -450,7 +433,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PublicDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xeb",
"Unit": "cpu_atom"
@@ -470,7 +452,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PublicDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfb",
"Unit": "cpu_atom"
@@ -491,7 +472,6 @@
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"PublicDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfb",
"Unit": "cpu_atom"
@@ -502,7 +482,6 @@
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.JCC",
"PublicDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x7e",
"Unit": "cpu_atom"
@@ -512,7 +491,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PublicDescription": "Counts the number of mispredicted near taken branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x80",
"Unit": "cpu_atom"
@@ -533,7 +511,6 @@
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"PublicDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xeb",
"Unit": "cpu_atom"
@@ -553,7 +530,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PublicDescription": "Counts the number of mispredicted near RET branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xf7",
"Unit": "cpu_atom"
@@ -564,7 +540,6 @@
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"PublicDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfe",
"Unit": "cpu_atom"
@@ -934,7 +909,7 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter. Available PDIST counters: 0",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.",
"SampleAfterValue": "2000003",
"Unit": "cpu_atom"
},
@@ -1126,7 +1101,6 @@
"Deprecated": "1",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.4K_ALIAS",
"PublicDescription": "This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_atom"
@@ -1136,7 +1110,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ADDRESS_ALIAS",
"PublicDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_atom"
@@ -1156,7 +1129,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"PublicDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_atom"
@@ -1186,7 +1158,7 @@
"Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PREFETCH.SWPF",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. Available PDIST counters: 0",
"PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. Available PDIST counters: 0",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_core"
@@ -1306,7 +1278,7 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xe4",
"EventName": "MISC_RETIRED.LBR_INSERTS",
"PublicDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. This event is PDIR on GP0 and NPEBS on all other GPs [This event is alias to LBR_INSERTS.ANY] Available PDIST counters: 0",
"PublicDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. This event is PDIR on GP0 and NPEBS on all other GPs [This event is alias to LBR_INSERTS.ANY]",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_atom"
@@ -1681,7 +1653,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "TOPDOWN_RETIRING.ALL",
"PublicDescription": "Counts the total number of consumed retirement slots. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"Unit": "cpu_atom"
},
@@ -1933,7 +1904,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.ALL",
"PublicDescription": "Counts the total number of uops retired. Available PDIST counters: 0",
"SampleAfterValue": "2000003",
"Unit": "cpu_atom"
},
@@ -1963,7 +1933,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.IDIV",
"PublicDescription": "Counts the number of integer divide uops retired. Available PDIST counters: 0",
"SampleAfterValue": "2000003",
"UMask": "0x10",
"Unit": "cpu_atom"
@@ -1973,7 +1942,7 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MS",
"PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows. Available PDIST counters: 0",
"PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
"SampleAfterValue": "2000003",
"UMask": "0x1",
"Unit": "cpu_atom"
@@ -2030,7 +1999,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.X87",
"PublicDescription": "Counts the number of x87 uops retired, includes those in MS flows. Available PDIST counters: 0",
"SampleAfterValue": "2000003",
"UMask": "0x2",
"Unit": "cpu_atom"

3
tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json
View File

@@ -266,7 +266,6 @@
"Deprecated": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
"PublicDescription": "This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x13",
"Unit": "cpu_atom"
@@ -278,7 +277,6 @@
"Deprecated": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
"PublicDescription": "This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS_LOADS Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x11",
"Unit": "cpu_atom"
@@ -290,7 +288,6 @@
"Deprecated": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
"PublicDescription": "This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS_STORES Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x12",
"Unit": "cpu_atom"

52
tools/perf/pmu-events/arch/x86/alderlaken/cache.json
View File

@@ -118,7 +118,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
"PublicDescription": "Counts the number of load uops retired that hit in DRAM. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
@@ -128,7 +127,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
"PublicDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
@@ -138,7 +136,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PublicDescription": "Counts the number of load uops retired that hit in the L1 data cache. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
@@ -148,7 +145,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"PublicDescription": "Counts the number of load uops retired that miss in the L1 data cache. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
@@ -158,7 +154,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PublicDescription": "Counts the number of load uops retired that hit in the L2 cache. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
@@ -168,7 +163,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PublicDescription": "Counts the number of load uops retired that miss in the L2 cache. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
@@ -178,7 +172,6 @@
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"PublicDescription": "Counts the number of load uops retired that hit in the L3 cache. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
@@ -188,7 +181,6 @@
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_UOPS_RETIRED_MISC.HIT_E_F",
"PublicDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required, and non-modified data was forwarded. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
@@ -198,7 +190,6 @@
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_UOPS_RETIRED_MISC.L3_MISS",
"PublicDescription": "Counts the number of load uops retired that miss in the L3 cache. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x20"
},
@@ -240,7 +231,7 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PublicDescription": "Counts the total number of load uops retired. Available PDIST counters: 0",
"PublicDescription": "Counts the total number of load uops retired.",
"SampleAfterValue": "200003",
"UMask": "0x81"
},
@@ -250,103 +241,103 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PublicDescription": "Counts the total number of store uops retired. Available PDIST counters: 0",
"PublicDescription": "Counts the total number of store uops retired.",
"SampleAfterValue": "200003",
"UMask": "0x82"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
@@ -356,7 +347,6 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PublicDescription": "Counts the number of load uops retired that performed one or more locks. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x21"
},
@@ -366,7 +356,6 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PublicDescription": "Counts the number of retired split load uops. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
@@ -376,7 +365,6 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS",
"PublicDescription": "Counts the total number of load and store uops retired that missed in the second level TLB. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x13"
},
@@ -386,7 +374,6 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
"PublicDescription": "Counts the number of load ops retired that miss in the second Level TLB. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x11"
},
@@ -396,7 +383,6 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"PublicDescription": "Counts the number of store ops retired that miss in the second level TLB. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x12"
},
@@ -406,7 +392,7 @@
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
"PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly. Available PDIST counters: 0",
"PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x6"
},

1
tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json
View File

@@ -29,7 +29,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.FPDIV",
"PublicDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt). Available PDIST counters: 0",
"SampleAfterValue": "2000003",
"UMask": "0x8"
}

1
tools/perf/pmu-events/arch/x86/alderlaken/other.json
View File

@@ -5,7 +5,6 @@
"Deprecated": "1",
"EventCode": "0xe4",
"EventName": "LBR_INSERTS.ANY",
"PublicDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS] Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},

42
tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json
View File

@@ -54,7 +54,7 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for. Available PDIST counters: 0",
"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
"SampleAfterValue": "200003"
},
{
@@ -63,7 +63,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.CALL",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xf9"
},
@@ -72,7 +71,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PublicDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
@@ -81,7 +79,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PublicDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
@@ -90,7 +87,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PublicDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xbf"
},
@@ -99,7 +95,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PublicDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
@@ -108,7 +103,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT_CALL",
"PublicDescription": "Counts the number of near indirect CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
@@ -118,7 +112,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
@@ -128,7 +121,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.JCC",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
@@ -137,7 +129,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PublicDescription": "Counts the number of near CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xf9"
},
@@ -146,7 +137,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PublicDescription": "Counts the number of near RET branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
@@ -155,7 +145,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PublicDescription": "Counts the number of near taken branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xc0"
},
@@ -165,7 +154,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
@@ -174,7 +162,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PublicDescription": "Counts the number of near relative CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfd"
},
@@ -184,7 +171,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.RETURN",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
@@ -194,7 +180,6 @@
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
@@ -203,7 +188,7 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. Available PDIST counters: 0",
"PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
"SampleAfterValue": "200003"
},
{
@@ -211,7 +196,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PublicDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
@@ -220,7 +204,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
"PublicDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
@@ -229,7 +212,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PublicDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
@@ -238,7 +220,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PublicDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
@@ -248,7 +229,6 @@
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"PublicDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
@@ -258,7 +238,6 @@
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.JCC",
"PublicDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
@@ -267,7 +246,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PublicDescription": "Counts the number of mispredicted near taken branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
@@ -277,7 +255,6 @@
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"PublicDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
@@ -286,7 +263,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PublicDescription": "Counts the number of mispredicted near RET branch instructions retired. Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
@@ -296,7 +272,6 @@
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"PublicDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
@@ -371,7 +346,7 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter. Available PDIST counters: 0",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.",
"SampleAfterValue": "2000003"
},
{
@@ -380,7 +355,6 @@
"Deprecated": "1",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.4K_ALIAS",
"PublicDescription": "This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
@@ -389,7 +363,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ADDRESS_ALIAS",
"PublicDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
@@ -398,7 +371,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"PublicDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
@@ -448,7 +420,7 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xe4",
"EventName": "MISC_RETIRED.LBR_INSERTS",
"PublicDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. This event is PDIR on GP0 and NPEBS on all other GPs [This event is alias to LBR_INSERTS.ANY] Available PDIST counters: 0",
"PublicDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. This event is PDIR on GP0 and NPEBS on all other GPs [This event is alias to LBR_INSERTS.ANY]",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
@@ -651,7 +623,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "TOPDOWN_RETIRING.ALL",
"PublicDescription": "Counts the total number of consumed retirement slots. Available PDIST counters: 0",
"SampleAfterValue": "1000003"
},
{
@@ -667,7 +638,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.ALL",
"PublicDescription": "Counts the total number of uops retired. Available PDIST counters: 0",
"SampleAfterValue": "2000003"
},
{
@@ -675,7 +645,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.IDIV",
"PublicDescription": "Counts the number of integer divide uops retired. Available PDIST counters: 0",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
@@ -684,7 +653,7 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MS",
"PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows. Available PDIST counters: 0",
"PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
@@ -693,7 +662,6 @@
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.X87",
"PublicDescription": "Counts the number of x87 uops retired, includes those in MS flows. Available PDIST counters: 0",
"SampleAfterValue": "2000003",
"UMask": "0x2"
}

3
tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json
View File

@@ -57,7 +57,6 @@
"Deprecated": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
"PublicDescription": "This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x13"
},
@@ -68,7 +67,6 @@
"Deprecated": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
"PublicDescription": "This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS_LOADS Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x11"
},
@@ -79,7 +77,6 @@
"Deprecated": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
"PublicDescription": "This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS_STORES Available PDIST counters: 0",
"SampleAfterValue": "200003",
"UMask": "0x12"
}

13
tools/perf/pmu-events/arch/x86/arrowlake/cache.json
View File

@@ -237,7 +237,7 @@
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of L2 Cache Accesses that miss the L2 and get BBL reject short and long rejects (includes those counted in L2_reject_XQ.any), per core event",
"BriefDescription": "Counts the number of L2 Cache Accesses that miss the L2 and get BBL reject short and long rejects, per core event",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_REQUEST.REJECTS",
@@ -728,6 +728,17 @@
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x101",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts retired load instructions with at least one uop that hit in the Level 0 of the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT_L0",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the Level 0 of the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. Available PDIST counters: 0",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_core"
},

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