arm64: dts: ti: Disable clock output of the ethernet PHY

The clock on the ethernet1 PHY is turned on by default. This turns
the clock off as we do not use it.

Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20240119225257.403222-1-nmorrisson@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Nathan Morrisson
2024-01-19 14:52:57 -08:00
committed by Vignesh Raghavendra
parent 28e4e32327
commit f4ee6882ef

View File

@@ -222,6 +222,7 @@ &cpsw3g_mdio {
cpsw3g_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <3>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};