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arm64: dts: exynos: Update cache properties

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The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221123092449.88097-2-pierre.gondois@arm.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Pierre Gondois
2022-11-23 10:24:44 +01:00
committed by Krzysztof Kozlowski
parent 1b929c02af
commit f3de853008
2 changed files with 6 additions and 0 deletions
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4
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View File

@@ -226,6 +226,8 @@ cpu7: cpu@3 {
cluster_a57_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -233,6 +235,8 @@ cluster_a57_l2: l2-cache0 {
cluster_a53_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;

2
arch/arm64/boot/dts/exynos/exynos7.dtsi
View File

@@ -107,6 +107,8 @@ cpu_atlas3: cpu@3 {
atlas_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;