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dt-bindings: clock: qcom: Add Qualcomm Shikra SoC Global Clock Controller

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Add device tree bindings for the global clock controller on Qualcomm
Shikra SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260608-shikra-gcc-rpmcc-clks-v5-2-94cefe092ee3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Imran Shaik
2026-06-08 17:51:50 +05:30
committed by Bjorn Andersson
parent a10eafcfc6
commit f390a1fac1
2 changed files with 333 additions and 0 deletions
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70
Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,shikra-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Global Clock & Reset Controller on Qualcomm Shikra SoC
maintainers:
- Imran Shaik <imran.shaik@oss.qualcomm.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Global clock control module provides the clocks, resets and power
domains on Qualcomm Shikra SoC platform.
See also: include/dt-bindings/clock/qcom,shikra-gcc.h
properties:
compatible:
const: qcom,shikra-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: EMAC0 sgmiiphy mac rclk source
- description: EMAC0 sgmiiphy mac tclk source
- description: EMAC1 sgmiiphy mac rclk source
- description: EMAC1 sgmiiphy mac tclk source
- description: PCIE Pipe clock source
- description: USB3 phy wrapper pipe clock source
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@1400000 {
compatible = "qcom,shikra-gcc";
reg = <0x01400000 0x1f0000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<&emac0_sgmiiphy_rclk>,
<&emac0_sgmiiphy_tclk>,
<&emac1_sgmiiphy_rclk>,
<&emac1_sgmiiphy_tclk>,
<&pcie_pipe_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
power-domains = <&rpmpd RPMPD_VDDCX>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...

263
include/dt-bindings/clock/qcom,shikra-gcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H
/* GCC clocks */
#define GPLL0 0
#define GPLL0_OUT_AUX2 1
#define GPLL1 2
#define GPLL10 3
#define GPLL11 4
#define GPLL12 5
#define GPLL12_OUT_AUX2 6
#define GPLL3 7
#define GPLL3_OUT_MAIN 8
#define GPLL4 9
#define GPLL5 10
#define GPLL6 11
#define GPLL6_OUT_MAIN 12
#define GPLL7 13
#define GPLL8 14
#define GPLL8_OUT_MAIN 15
#define GPLL9 16
#define GPLL9_OUT_MAIN 17
#define GCC_AHB2PHY_CSI_CLK 18
#define GCC_AHB2PHY_USB_CLK 19
#define GCC_BOOT_ROM_AHB_CLK 20
#define GCC_CAM_THROTTLE_NRT_CLK 21
#define GCC_CAM_THROTTLE_RT_CLK 22
#define GCC_CAMERA_AHB_CLK 23
#define GCC_CAMERA_XO_CLK 24
#define GCC_CAMSS_AXI_CLK 25
#define GCC_CAMSS_AXI_CLK_SRC 26
#define GCC_CAMSS_CAMNOC_ATB_CLK 27
#define GCC_CAMSS_CAMNOC_DRAGONLINK_ATB_CLK 28
#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 29
#define GCC_CAMSS_CCI_0_CLK 30
#define GCC_CAMSS_CCI_CLK_SRC 31
#define GCC_CAMSS_CPHY_0_CLK 32
#define GCC_CAMSS_CPHY_1_CLK 33
#define GCC_CAMSS_CSI0PHYTIMER_CLK 34
#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 35
#define GCC_CAMSS_CSI1PHYTIMER_CLK 36
#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 37
#define GCC_CAMSS_MCLK0_CLK 38
#define GCC_CAMSS_MCLK0_CLK_SRC 39
#define GCC_CAMSS_MCLK1_CLK 40
#define GCC_CAMSS_MCLK1_CLK_SRC 41
#define GCC_CAMSS_MCLK2_CLK 42
#define GCC_CAMSS_MCLK2_CLK_SRC 43
#define GCC_CAMSS_MCLK3_CLK 44
#define GCC_CAMSS_MCLK3_CLK_SRC 45
#define GCC_CAMSS_NRT_AXI_CLK 46
#define GCC_CAMSS_OPE_AHB_CLK 47
#define GCC_CAMSS_OPE_AHB_CLK_SRC 48
#define GCC_CAMSS_OPE_CLK 49
#define GCC_CAMSS_OPE_CLK_SRC 50
#define GCC_CAMSS_RT_AXI_CLK 51
#define GCC_CAMSS_TFE_0_CLK 52
#define GCC_CAMSS_TFE_0_CLK_SRC 53
#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 54
#define GCC_CAMSS_TFE_0_CSID_CLK 55
#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 56
#define GCC_CAMSS_TFE_1_CLK 57
#define GCC_CAMSS_TFE_1_CLK_SRC 58
#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 59
#define GCC_CAMSS_TFE_1_CSID_CLK 60
#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 61
#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 62
#define GCC_CAMSS_TOP_AHB_CLK 63
#define GCC_CAMSS_TOP_AHB_CLK_SRC 64
#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 65
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 66
#define GCC_DDRSS_GPU_AXI_CLK 67
#define GCC_DDRSS_MEMNOC_PCIE_SF_CLK 68
#define GCC_DISP_AHB_CLK 69
#define GCC_DISP_GPLL0_CLK_SRC 70
#define GCC_DISP_GPLL0_DIV_CLK_SRC 71
#define GCC_DISP_HF_AXI_CLK 72
#define GCC_DISP_THROTTLE_CORE_CLK 73
#define GCC_DISP_XO_CLK 74
#define GCC_EMAC0_AHB_CLK 75
#define GCC_EMAC0_AXI_CLK 76
#define GCC_EMAC0_AXI_CLK_SRC 77
#define GCC_EMAC0_AXI_SYS_NOC_CLK 78
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 79
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 80
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 81
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 82
#define GCC_EMAC0_PHY_AUX_CLK 83
#define GCC_EMAC0_PHY_AUX_CLK_SRC 84
#define GCC_EMAC0_PTP_CLK 85
#define GCC_EMAC0_PTP_CLK_SRC 86
#define GCC_EMAC0_RGMII_CLK 87
#define GCC_EMAC0_RGMII_CLK_SRC 88
#define GCC_EMAC1_AHB_CLK 89
#define GCC_EMAC1_AXI_CLK 90
#define GCC_EMAC1_AXI_CLK_SRC 91
#define GCC_EMAC1_AXI_SYS_NOC_CLK 92
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 93
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 94
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 95
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 96
#define GCC_EMAC1_PHY_AUX_CLK 97
#define GCC_EMAC1_PHY_AUX_CLK_SRC 98
#define GCC_EMAC1_PTP_CLK 99
#define GCC_EMAC1_PTP_CLK_SRC 100
#define GCC_EMAC1_RGMII_CLK 101
#define GCC_EMAC1_RGMII_CLK_SRC 102
#define GCC_GP1_CLK 103
#define GCC_GP1_CLK_SRC 104
#define GCC_GP2_CLK 105
#define GCC_GP2_CLK_SRC 106
#define GCC_GP3_CLK 107
#define GCC_GP3_CLK_SRC 108
#define GCC_GPU_CFG_AHB_CLK 109
#define GCC_GPU_GPLL0_CLK_SRC 110
#define GCC_GPU_GPLL0_DIV_CLK_SRC 111
#define GCC_GPU_IREF_CLK 112
#define GCC_GPU_MEMNOC_GFX_CLK 113
#define GCC_GPU_SMMU_VOTE_CLK 114
#define GCC_GPU_SNOC_DVM_GFX_CLK 115
#define GCC_GPU_THROTTLE_CORE_CLK 116
#define GCC_LPASS_CONFIG_CLK 117
#define GCC_LPASS_CORE_AXIM_CLK 118
#define GCC_MMU_TCU_VOTE_CLK 119
#define GCC_PCIE_AUX_CLK 120
#define GCC_PCIE_AUX_CLK_SRC 121
#define GCC_PCIE_AUX_PHY_CLK_SRC 122
#define GCC_PCIE_CFG_AHB_CLK 123
#define GCC_PCIE_CLKREF_EN 124
#define GCC_PCIE_MSTR_AXI_CLK 125
#define GCC_PCIE_PIPE_CLK 126
#define GCC_PCIE_PIPE_CLK_SRC 127
#define GCC_PCIE_RCHNG_PHY_CLK 128
#define GCC_PCIE_RCHNG_PHY_CLK_SRC 129
#define GCC_PCIE_SLEEP_CLK 130
#define GCC_PCIE_SLV_AXI_CLK 131
#define GCC_PCIE_SLV_Q2A_AXI_CLK 132
#define GCC_PCIE_TBU_CLK 133
#define GCC_PCIE_THROTTLE_CORE_CLK 134
#define GCC_PCIE_THROTTLE_XO_CLK 135
#define GCC_PCIE_TILE_AXI_SYS_NOC_CLK 136
#define GCC_PDM2_CLK 137
#define GCC_PDM2_CLK_SRC 138
#define GCC_PDM_AHB_CLK 139
#define GCC_PDM_XO4_CLK 140
#define GCC_PWM0_XO512_CLK 141
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 142
#define GCC_QMIP_CAMERA_RT_AHB_CLK 143
#define GCC_QMIP_DISP_AHB_CLK 144
#define GCC_QMIP_GPU_CFG_AHB_CLK 145
#define GCC_QMIP_PCIE_CFG_AHB_CLK 146
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 147
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 148
#define GCC_QUPV3_WRAP0_CORE_CLK 149
#define GCC_QUPV3_WRAP0_S0_CLK 150
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 151
#define GCC_QUPV3_WRAP0_S1_CLK 152
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 153
#define GCC_QUPV3_WRAP0_S2_CLK 154
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 155
#define GCC_QUPV3_WRAP0_S3_CLK 156
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 157
#define GCC_QUPV3_WRAP0_S4_CLK 158
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 159
#define GCC_QUPV3_WRAP0_S5_CLK 160
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 161
#define GCC_QUPV3_WRAP0_S6_CLK 162
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 163
#define GCC_QUPV3_WRAP0_S7_CLK 164
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 165
#define GCC_QUPV3_WRAP0_S8_CLK 166
#define GCC_QUPV3_WRAP0_S8_CLK_SRC 167
#define GCC_QUPV3_WRAP0_S9_CLK 168
#define GCC_QUPV3_WRAP0_S9_CLK_SRC 169
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 170
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 171
#define GCC_SDCC1_AHB_CLK 172
#define GCC_SDCC1_APPS_CLK 173
#define GCC_SDCC1_APPS_CLK_SRC 174
#define GCC_SDCC1_ICE_CORE_CLK 175
#define GCC_SDCC1_ICE_CORE_CLK_SRC 176
#define GCC_SDCC2_AHB_CLK 177
#define GCC_SDCC2_APPS_CLK 178
#define GCC_SDCC2_APPS_CLK_SRC 179
#define GCC_SYS_NOC_CPUSS_AHB_CLK 180
#define GCC_SYS_NOC_USB2_PRIM_AXI_CLK 181
#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 182
#define GCC_TSCSS_AHB_CLK 183
#define GCC_TSCSS_CLK_SRC 184
#define GCC_TSCSS_CNTR_CLK 185
#define GCC_TSCSS_ETU_CLK 186
#define GCC_UFS_CLKREF_EN 187
#define GCC_USB20_MASTER_CLK 188
#define GCC_USB20_MASTER_CLK_SRC 189
#define GCC_USB20_MOCK_UTMI_CLK 190
#define GCC_USB20_MOCK_UTMI_CLK_SRC 191
#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 192
#define GCC_USB20_SLEEP_CLK 193
#define GCC_USB30_PRIM_MASTER_CLK 194
#define GCC_USB30_PRIM_MASTER_CLK_SRC 195
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 196
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 197
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 198
#define GCC_USB30_PRIM_SLEEP_CLK 199
#define GCC_USB3_PRIM_CLKREF_EN 200
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 201
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 202
#define GCC_USB3_PRIM_PHY_PIPE_CLK 203
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 204
#define GCC_VCODEC0_AXI_CLK 205
#define GCC_VENUS_AHB_CLK 206
#define GCC_VENUS_CTL_AXI_CLK 207
#define GCC_VIDEO_AHB_CLK 208
#define GCC_VIDEO_AXI0_CLK 209
#define GCC_VIDEO_THROTTLE_CORE_CLK 210
#define GCC_VIDEO_VCODEC0_SYS_CLK 211
#define GCC_VIDEO_VENUS_CLK_SRC 212
#define GCC_VIDEO_VENUS_CTL_CLK 213
#define GCC_VIDEO_XO_CLK 214
/* GCC power domains */
#define GCC_CAMSS_TOP_GDSC 0
#define GCC_EMAC0_GDSC 1
#define GCC_EMAC1_GDSC 2
#define GCC_PCIE_GDSC 3
#define GCC_USB20_GDSC 4
#define GCC_USB30_PRIM_GDSC 5
#define GCC_VCODEC0_GDSC 6
#define GCC_VENUS_GDSC 7
/* GCC resets */
#define GCC_CAMSS_OPE_BCR 0
#define GCC_CAMSS_TFE_BCR 1
#define GCC_CAMSS_TOP_BCR 2
#define GCC_EMAC0_BCR 3
#define GCC_EMAC1_BCR 4
#define GCC_GPU_BCR 5
#define GCC_MMSS_BCR 6
#define GCC_PCIE_BCR 7
#define GCC_PCIE_PHY_BCR 8
#define GCC_PDM_BCR 9
#define GCC_QUPV3_WRAPPER_0_BCR 10
#define GCC_QUSB2PHY_PRIM_BCR 11
#define GCC_QUSB2PHY_SEC_BCR 12
#define GCC_SDCC1_BCR 13
#define GCC_SDCC2_BCR 14
#define GCC_TSCSS_BCR 15
#define GCC_USB20_BCR 16
#define GCC_USB30_PRIM_BCR 17
#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 18
#define GCC_USB3_DP_PHY_PRIM_BCR 19
#define GCC_USB3_PHY_PRIM_SP0_BCR 20
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 21
#define GCC_VCODEC0_BCR 22
#define GCC_VENUS_BCR 23
#define GCC_VIDEO_INTERFACE_BCR 24
#endif