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drm/amdgpu: add umc v12.0 ACA support
add umc v12.0 ACA driver support Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -444,12 +444,70 @@ const struct amdgpu_ras_block_hw_ops umc_v12_0_ras_hw_ops = {
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.query_ras_error_address = umc_v12_0_query_ras_error_address,
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};
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static int umc_v12_0_aca_bank_generate_report(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type,
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struct aca_bank_report *report, void *data)
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{
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struct amdgpu_device *adev = handle->adev;
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u64 status;
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int ret;
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ret = aca_bank_info_decode(bank, &report->info);
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if (ret)
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return ret;
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status = bank->regs[ACA_REG_IDX_STATUS];
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switch (type) {
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case ACA_ERROR_TYPE_UE:
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if (umc_v12_0_is_uncorrectable_error(adev, status)) {
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report->count[type] = 1;
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}
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break;
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case ACA_ERROR_TYPE_CE:
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if (umc_v12_0_is_correctable_error(adev, status)) {
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report->count[type] = 1;
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}
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct aca_bank_ops umc_v12_0_aca_bank_ops = {
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.aca_bank_generate_report = umc_v12_0_aca_bank_generate_report,
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};
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const struct aca_info umc_v12_0_aca_info = {
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.hwip = ACA_HWIP_TYPE_UMC,
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.mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK,
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.bank_ops = &umc_v12_0_aca_bank_ops,
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};
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static int umc_v12_0_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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int ret;
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ret = amdgpu_umc_ras_late_init(adev, ras_block);
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if (ret)
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return ret;
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ret = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__UMC,
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&umc_v12_0_aca_info, NULL);
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if (ret)
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return ret;
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return 0;
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}
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struct amdgpu_umc_ras umc_v12_0_ras = {
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.ras_block = {
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.hw_ops = &umc_v12_0_ras_hw_ops,
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.ras_late_init = umc_v12_0_ras_late_init,
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},
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.err_cnt_init = umc_v12_0_err_cnt_init,
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.query_ras_poison_mode = umc_v12_0_query_ras_poison_mode,
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.ecc_info_query_ras_error_count = umc_v12_0_ecc_info_query_ras_error_count,
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.ecc_info_query_ras_error_address = umc_v12_0_ecc_info_query_ras_error_address,
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};
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