mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-14 04:09:18 -04:00
Merge branch 'arm64-for-6.13' into arm64-for-6.14
Merge the arm64-for-6.13 branch into arm64-for-6.14, to carry forward the commits that were picked up late in the cycle but didn't make it into a pull request.
This commit is contained in:
Bjorn Andersson
@@ -23,7 +23,7 @@ description: |
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
|
||||
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1e)[0-9]+.*$"
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@@ -32,6 +32,7 @@ properties:
|
||||
oneOf:
|
||||
# Preferred naming style for compatibles of SoC components:
|
||||
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
|
||||
- pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
|
||||
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
|
||||
|
||||
# Legacy namings - variations of existing patterns/compatibles are OK,
|
||||
|
||||
@@ -19,27 +19,37 @@ description: |
|
||||
|
||||
apq8016
|
||||
apq8026
|
||||
apq8064
|
||||
apq8074
|
||||
apq8084
|
||||
apq8094
|
||||
apq8096
|
||||
ipq4018
|
||||
ipq4019
|
||||
ipq5018
|
||||
ipq5332
|
||||
ipq5424
|
||||
ipq6018
|
||||
ipq8064
|
||||
ipq8074
|
||||
ipq9574
|
||||
mdm9615
|
||||
msm8226
|
||||
msm8660
|
||||
msm8916
|
||||
msm8926
|
||||
msm8929
|
||||
msm8939
|
||||
msm8953
|
||||
msm8956
|
||||
msm8960
|
||||
msm8974
|
||||
msm8974pro
|
||||
msm8976
|
||||
msm8992
|
||||
msm8994
|
||||
msm8996
|
||||
msm8996pro
|
||||
msm8998
|
||||
qcs404
|
||||
qcs8550
|
||||
@@ -53,6 +63,7 @@ description: |
|
||||
sa8155p
|
||||
sa8540p
|
||||
sa8775p
|
||||
sar2130p
|
||||
sc7180
|
||||
sc7280
|
||||
sc8180x
|
||||
@@ -84,6 +95,7 @@ description: |
|
||||
sm8450
|
||||
sm8550
|
||||
sm8650
|
||||
x1e78100
|
||||
x1e80100
|
||||
|
||||
There are many devices in the list below that run the standard ChromeOS
|
||||
@@ -352,6 +364,11 @@ properties:
|
||||
- qcom,ipq5332-ap-mi01.9
|
||||
- const: qcom,ipq5332
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq5424-rdp466
|
||||
- const: qcom,ipq5424
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- mikrotik,rb3011
|
||||
@@ -408,6 +425,12 @@ properties:
|
||||
- qcom,qru1000-idp
|
||||
- const: qcom,qru1000
|
||||
|
||||
- description: Qualcomm AR2 Gen1 platform
|
||||
items:
|
||||
- enum:
|
||||
- qcom,qar2130p
|
||||
- const: qcom,sar2130p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- acer,aspire1
|
||||
@@ -1064,6 +1087,12 @@ properties:
|
||||
- qcom,sm8650-qrd
|
||||
- const: qcom,sm8650
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,x1e001de-devkit
|
||||
- const: qcom,x1e001de
|
||||
- const: qcom,x1e80100
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,thinkpad-t14s
|
||||
|
||||
@@ -3,6 +3,8 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
|
||||
|
||||
apq8016-sbc-usb-host-dtbs := apq8016-sbc.dtb apq8016-sbc-usb-host.dtbo
|
||||
|
||||
dtb-$(CONFIG_ARCH_QCOM) += sar2130p-qar2130p.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-usb-host.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3-camera-mezzanine.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += apq8016-schneider-hmibsc.dtb
|
||||
@@ -16,6 +18,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp474.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += ipq5424-rdp466.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
|
||||
@@ -278,6 +281,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb
|
||||
|
||||
59
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
Normal file
59
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
Normal file
@@ -0,0 +1,59 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
||||
/*
|
||||
* IPQ5424 RDP466 board device tree source
|
||||
*
|
||||
* Copyright (c) 2024 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq5424.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ5424 RDP466";
|
||||
compatible = "qcom,ipq5424-rdp466", "qcom,ipq5424";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
};
|
||||
};
|
||||
|
||||
&sleep_clk {
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
sdc_default_state: sdc-default-state {
|
||||
clk-pins {
|
||||
pins = "gpio5";
|
||||
function = "sdc_clk";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cmd-pins {
|
||||
pins = "gpio4";
|
||||
function = "sdc_cmd";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||
function = "sdc_data";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xo_board {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
305
arch/arm64/boot/dts/qcom/ipq5424.dtsi
Normal file
305
arch/arm64/boot/dts/qcom/ipq5424.dtsi
Normal file
@@ -0,0 +1,305 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* IPQ5424 device tree source
|
||||
*
|
||||
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
|
||||
#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
clocks {
|
||||
sleep_clk: sleep-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
xo_board: xo-board-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpus: cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2_0>;
|
||||
l2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&l3_0>;
|
||||
|
||||
l3_0: l3-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
enable-method = "psci";
|
||||
reg = <0x100>;
|
||||
next-level-cache = <&l2_100>;
|
||||
|
||||
l2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
enable-method = "psci";
|
||||
reg = <0x200>;
|
||||
next-level-cache = <&l2_200>;
|
||||
|
||||
l2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
enable-method = "psci";
|
||||
reg = <0x300>;
|
||||
next-level-cache = <&l2_300>;
|
||||
|
||||
l2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* We expect the bootloader to fill in the size */
|
||||
reg = <0x0 0x80000000 0x0 0x0>;
|
||||
};
|
||||
|
||||
pmu-a55 {
|
||||
compatible = "arm,cortex-a55-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pmu-dsu {
|
||||
compatible = "arm,dsu-pmu";
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
|
||||
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
tz@8a600000 {
|
||||
reg = <0x0 0x8a600000 0x0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
smem@8a800000 {
|
||||
compatible = "qcom,smem";
|
||||
reg = <0x0 0x8a800000 0x0 0x32000>;
|
||||
no-map;
|
||||
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0 0 0 0 0x10 0>;
|
||||
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,ipq5424-tlmm";
|
||||
reg = <0 0x01000000 0 0x300000>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 50>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
uart1_pins: uart1-state {
|
||||
pins = "gpio43", "gpio44";
|
||||
function = "uart1";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
gcc: clock-controller@1800000 {
|
||||
compatible = "qcom,ipq5424-gcc";
|
||||
reg = <0 0x01800000 0 0x40000>;
|
||||
clocks = <&xo_board>,
|
||||
<&sleep_clk>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
tcsr_mutex: hwlock@1905000 {
|
||||
compatible = "qcom,tcsr-mutex";
|
||||
reg = <0 0x01905000 0 0x20000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
qupv3: geniqup@1ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0 0x01ac0000 0 0x2000>;
|
||||
ranges;
|
||||
clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
|
||||
<&gcc GCC_QUPV3_AHB_SLV_CLK>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
uart1: serial@1a84000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0 0x01a84000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_UART1_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhc: mmc@7804000 {
|
||||
compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
|
||||
reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>;
|
||||
reg-names = "hc", "cqhci";
|
||||
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
||||
<&gcc GCC_SDCC1_APPS_CLK>,
|
||||
<&xo_board>;
|
||||
clock-names = "iface", "core", "xo";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@f200000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0 0xf200000 0 0x10000>, /* GICD */
|
||||
<0 0xf240000 0 0x80000>; /* GICR * 4 regions */
|
||||
#interrupt-cells = <0x3>;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x20000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
mbi-ranges = <672 128>;
|
||||
msi-controller;
|
||||
};
|
||||
|
||||
timer@f420000 {
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0 0xf420000 0 0x1000>;
|
||||
ranges = <0 0 0 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
frame@f421000 {
|
||||
reg = <0xf421000 0x1000>,
|
||||
<0xf422000 0x1000>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
frame-number = <0>;
|
||||
};
|
||||
|
||||
frame@f423000 {
|
||||
reg = <0xf423000 0x1000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
frame-number = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f425000 {
|
||||
reg = <0xf425000 0x1000>,
|
||||
<0xf426000 0x1000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
frame-number = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f427000 {
|
||||
reg = <0xf427000 0x1000>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
frame-number = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f429000 {
|
||||
reg = <0xf429000 0x1000>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
frame-number = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f42b000 {
|
||||
reg = <0xf42b000 0x1000>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
frame-number = <5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f42d000 {
|
||||
reg = <0xf42d000 0x1000>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
frame-number = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
558
arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
Normal file
558
arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
Normal file
@@ -0,0 +1,558 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024, Linaro Limited
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "sar2130p.dtsi"
|
||||
#include "pm8150.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Snapdragon AR2 Gen1 Smart Viewer Development Kit";
|
||||
compatible = "qcom,qar2130p", "qcom,sar2130p";
|
||||
chassis-type = "embedded";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart11;
|
||||
serial1 = &uart7;
|
||||
i2c0 = &i2c8;
|
||||
i2c1 = &i2c10;
|
||||
mmc1 = &sdhc_1;
|
||||
spi0 = &spi0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
vph_pwr: regulator-vph-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* pm3003a on I2C0, should not be controlled */
|
||||
vreg_ext_1p3: regulator-ext-1p3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_ext_1p3";
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vph_pwr>;
|
||||
};
|
||||
|
||||
/* EBI rail, used as LDO input, can not be part of PMIC config */
|
||||
vreg_s10a_0p89: regulator-s10a-0p89 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_s10a_0p89";
|
||||
regulator-min-microvolt = <890000>;
|
||||
regulator-max-microvolt = <890000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vph_pwr>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
sar2130p-thermal {
|
||||
thermal-sensors = <&pm8150_adc_tm 1>;
|
||||
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <100000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wifi-thermal {
|
||||
thermal-sensors = <&pm8150_adc_tm 2>;
|
||||
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <52000>;
|
||||
hysteresis = <4000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
xo-thermal {
|
||||
thermal-sensors = <&pm8150_adc_tm 0>;
|
||||
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <50000>;
|
||||
hysteresis = <4000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wcn7850-pmu {
|
||||
compatible = "qcom,wcn7850-pmu";
|
||||
|
||||
pinctrl-0 = <&wlan_en_state>, <&bt_en_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wlan-enable-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
|
||||
bt-enable-gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vdd-supply = <&vreg_s4a_0p95>;
|
||||
vddio-supply = <&vreg_l15a_1p8>;
|
||||
vddaon-supply = <&vreg_s4a_0p95>;
|
||||
vdddig-supply = <&vreg_s4a_0p95>;
|
||||
vddrfa1p2-supply = <&vreg_s4a_0p95>;
|
||||
vddrfa1p8-supply = <&vreg_s5a_1p88>;
|
||||
|
||||
regulators {
|
||||
vreg_pmu_rfa_cmn: ldo0 {
|
||||
regulator-name = "vreg_pmu_rfa_cmn";
|
||||
};
|
||||
|
||||
vreg_pmu_aon_0p59: ldo1 {
|
||||
regulator-name = "vreg_pmu_aon_0p59";
|
||||
};
|
||||
|
||||
vreg_pmu_wlcx_0p8: ldo2 {
|
||||
regulator-name = "vreg_pmu_wlcx_0p8";
|
||||
};
|
||||
|
||||
vreg_pmu_wlmx_0p85: ldo3 {
|
||||
regulator-name = "vreg_pmu_wlmx_0p85";
|
||||
};
|
||||
|
||||
vreg_pmu_btcmx_0p85: ldo4 {
|
||||
regulator-name = "vreg_pmu_btcmx_0p85";
|
||||
};
|
||||
|
||||
vreg_pmu_rfa_0p8: ldo5 {
|
||||
regulator-name = "vreg_pmu_rfa_0p8";
|
||||
};
|
||||
|
||||
vreg_pmu_rfa_1p2: ldo6 {
|
||||
regulator-name = "vreg_pmu_rfa_1p2";
|
||||
};
|
||||
|
||||
vreg_pmu_rfa_1p8: ldo7 {
|
||||
regulator-name = "vreg_pmu_rfa_1p8";
|
||||
};
|
||||
|
||||
vreg_pmu_pcie_0p9: ldo8 {
|
||||
regulator-name = "vreg_pmu_pcie_0p9";
|
||||
};
|
||||
|
||||
vreg_pmu_pcie_1p8: ldo9 {
|
||||
regulator-name = "vreg_pmu_pcie_1p8";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
regulators-0 {
|
||||
compatible = "qcom,pm8150-rpmh-regulators";
|
||||
qcom,pmic-id = "a";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
vdd-l1-l8-l11-supply = <&vreg_s4a_0p95>;
|
||||
vdd-l3-l4-l5-l18-supply = <&vreg_ext_1p3>;
|
||||
vdd-l6-l9-supply = <&vreg_s10a_0p89>;
|
||||
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p88>;
|
||||
|
||||
vreg_s4a_0p95: smps6 {
|
||||
regulator-name = "vreg_s4a_0p95";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1170000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s5a_1p88: smps5 {
|
||||
regulator-name = "vreg_s5a_1p88";
|
||||
regulator-min-microvolt = <1856000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1a_0p91: ldo1 {
|
||||
regulator-name = "vreg_l1a_0p91";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2a_3p1: ldo2 {
|
||||
regulator-name = "vreg_l2a_3p1";
|
||||
regulator-min-microvolt = <3080000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3a_1p2: ldo3 {
|
||||
regulator-name = "vreg_l3a_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
/* ldo4 1.26 - system ? */
|
||||
|
||||
vreg_l5a_1p13: ldo5 {
|
||||
regulator-name = "vreg_l5a_1p13";
|
||||
regulator-min-microvolt = <1128000>;
|
||||
regulator-max-microvolt = <1170000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6a_0p6: ldo6 {
|
||||
regulator-name = "vreg_l6a_0p6";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <650000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7a_1p8: ldo7 {
|
||||
regulator-name = "vreg_l7a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8a_0p88: ldo8 {
|
||||
regulator-name = "vreg_l8a_0p88";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
/* ldo9 - LCX */
|
||||
|
||||
vreg_l10a_2p95: ldo10 {
|
||||
regulator-name = "vreg_l10a_2p95";
|
||||
regulator-min-microvolt = <2952000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
/* ldo11 - LMX */
|
||||
|
||||
vreg_l12a_1p8: ldo12 {
|
||||
regulator-name = "vreg_l12a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
/* no ldo13 */
|
||||
|
||||
vreg_l14a_1p8: ldo14 {
|
||||
regulator-name = "vreg_l14a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l15a_1p8: ldo15 {
|
||||
regulator-name = "vreg_l15a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
/* no ldo16 - system */
|
||||
|
||||
vreg_l17a_3p26: ldo17 {
|
||||
regulator-name = "vreg_l17a_3p26";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l18a_1p2: ldo18 {
|
||||
regulator-name = "vreg_l18a_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&gpi_dma0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpi_dma1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sar2130p/a620_zap.mbn";
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_resin {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c8 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
ptn3222: redriver@4f {
|
||||
compatible = "nxp,ptn3222";
|
||||
reg = <0x4f>;
|
||||
|
||||
reset-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vdd3v3-supply = <&vreg_l2a_3p1>;
|
||||
vdd1v8-supply = <&vreg_l15a_1p8>;
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcieport0 {
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
||||
vddaon-supply = <&vreg_pmu_aon_0p59>;
|
||||
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
|
||||
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
|
||||
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
|
||||
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
|
||||
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
|
||||
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
|
||||
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
|
||||
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0_phy {
|
||||
vdda-phy-supply = <&vreg_l8a_0p88>;
|
||||
vdda-pll-supply = <&vreg_l3a_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8150_adc {
|
||||
channel@4c {
|
||||
reg = <ADC5_XO_THERM_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
label = "xo_therm";
|
||||
};
|
||||
|
||||
channel@4d {
|
||||
reg = <ADC5_AMUX_THM1_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,pre-scaling = <1 1>;
|
||||
label = "skin_therm";
|
||||
};
|
||||
|
||||
channel@4e {
|
||||
/* msm-5.10 uses ADC5_AMUX_THM2 / 0x0e, although there is a pullup */
|
||||
reg = <ADC5_AMUX_THM2_100K_PU>;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,pre-scaling = <1 1>;
|
||||
label = "wifi_therm";
|
||||
};
|
||||
};
|
||||
|
||||
&pm8150_adc_tm {
|
||||
status = "okay";
|
||||
|
||||
xo-therm@0 {
|
||||
reg = <0>;
|
||||
io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
skin-therm@1 {
|
||||
reg = <1>;
|
||||
io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
wifi-therm@2 {
|
||||
reg = <2>;
|
||||
/* msm-5.10 uses ADC5_AMUX_THM2, although there is a pullup */
|
||||
io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/sar2130p/adsp.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
vmmc-supply = <&vreg_l10a_2p95>;
|
||||
vqmmc-supply = <&vreg_l7a_1p8>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
bt_en_state: bt-enable-state {
|
||||
pins = "gpio46";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie0_default_state: pcie0-default-state {
|
||||
perst-pins {
|
||||
pins = "gpio55";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
clkreq-pins {
|
||||
pins = "gpio56";
|
||||
function = "pcie0_clkreqn";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
wake-pins {
|
||||
pins = "gpio57";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_default_state: pcie1-default-state {
|
||||
perst-pins {
|
||||
pins = "gpio58";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
clkreq-pins {
|
||||
pins = "gpio59";
|
||||
function = "pcie1_clkreqn";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
wake-pins {
|
||||
pins = "gpio60";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
wlan_en_state: wlan-enable-state {
|
||||
pins = "gpio45";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "qcom,wcn7850-bt";
|
||||
|
||||
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
|
||||
vddaon-supply = <&vreg_pmu_aon_0p59>;
|
||||
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
|
||||
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
|
||||
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
|
||||
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
|
||||
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
|
||||
|
||||
max-speed = <3200000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart11 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
vdd-supply = <&vreg_l8a_0p88>;
|
||||
vdda12-supply = <&vreg_l3a_1p2>;
|
||||
|
||||
phys = <&ptn3222>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dp_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l3a_1p2>;
|
||||
vdda-pll-supply = <&vreg_l1a_0p91>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
3123
arch/arm64/boot/dts/qcom/sar2130p.dtsi
Normal file
3123
arch/arm64/boot/dts/qcom/sar2130p.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
1343
arch/arm64/boot/dts/qcom/x1e001de-devkit.dts
Normal file
1343
arch/arm64/boot/dts/qcom/x1e001de-devkit.dts
Normal file
File diff suppressed because it is too large
Load Diff
@@ -328,6 +328,14 @@ vreg_l3j_0p8: ldo3 {
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
|
||||
zap-shader {
|
||||
firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcdxkmsuc8380.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
@@ -89,7 +89,15 @@ port@1 {
|
||||
reg = <1>;
|
||||
|
||||
pmic_glink_ss0_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss0_qmpphy_out>;
|
||||
remote-endpoint = <&retimer_ss0_ss_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
pmic_glink_ss0_con_sbu_in: endpoint {
|
||||
remote-endpoint = <&retimer_ss0_con_sbu_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -118,7 +126,15 @@ port@1 {
|
||||
reg = <1>;
|
||||
|
||||
pmic_glink_ss1_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss1_qmpphy_out>;
|
||||
remote-endpoint = <&retimer_ss1_ss_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
pmic_glink_ss1_con_sbu_in: endpoint {
|
||||
remote-endpoint = <&retimer_ss1_con_sbu_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -166,6 +182,102 @@ vreg_nvme: regulator-nvme {
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR0_1P15";
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
|
||||
gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&rtmr0_1p15_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR0_1P8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&rtmr0_1p8_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR0_3P3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&rtmr0_3p3_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR1_1P15";
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
|
||||
gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&rtmr1_1p15_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR1_1P8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&rtmr1_1p8_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR1_3P3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&rtmr1_3p3_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_vph_pwr: regulator-vph-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
@@ -492,9 +604,60 @@ keyboard@5 {
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
status = "disabled";
|
||||
/* PS8830 Retimer @0x8 */
|
||||
/* Unknown device @0x9 */
|
||||
status = "okay";
|
||||
|
||||
/* Right-side USB Type-C port */
|
||||
typec-mux@8 {
|
||||
compatible = "parade,ps8830";
|
||||
reg = <0x08>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_RF_CLK3>;
|
||||
clock-names = "xo";
|
||||
|
||||
vdd-supply = <&vreg_rtmr0_1p15>;
|
||||
vdd33-supply = <&vreg_rtmr0_3p3>;
|
||||
vdd33-cap-supply = <&vreg_rtmr0_3p3>;
|
||||
vddar-supply = <&vreg_rtmr0_1p15>;
|
||||
vddat-supply = <&vreg_rtmr0_1p15>;
|
||||
vddio-supply = <&vreg_rtmr0_1p8>;
|
||||
|
||||
reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&rtmr0_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
retimer-switch;
|
||||
orientation-switch;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
retimer_ss0_ss_out: endpoint {
|
||||
remote-endpoint = <&pmic_glink_ss0_ss_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
retimer_ss0_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss0_qmpphy_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
retimer_ss0_con_sbu_out: endpoint {
|
||||
remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
@@ -505,9 +668,61 @@ &i2c5 {
|
||||
|
||||
&i2c7 {
|
||||
clock-frequency = <400000>;
|
||||
status = "disabled";
|
||||
/* PS8830 Retimer @0x8 */
|
||||
/* Unknown device @0x9 */
|
||||
status = "okay";
|
||||
|
||||
/* Left-side USB Type-C port */
|
||||
typec-mux@8 {
|
||||
compatible = "parade,ps8830";
|
||||
reg = <0x8>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_RF_CLK4>;
|
||||
clock-names = "xo";
|
||||
|
||||
vdd-supply = <&vreg_rtmr1_1p15>;
|
||||
vdd33-supply = <&vreg_rtmr1_3p3>;
|
||||
vdd33-cap-supply = <&vreg_rtmr1_3p3>;
|
||||
vddar-supply = <&vreg_rtmr1_1p15>;
|
||||
vddat-supply = <&vreg_rtmr1_1p15>;
|
||||
vddio-supply = <&vreg_rtmr1_1p8>;
|
||||
|
||||
reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&rtmr1_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
retimer-switch;
|
||||
orientation-switch;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
retimer_ss1_ss_out: endpoint {
|
||||
remote-endpoint = <&pmic_glink_ss1_ss_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
retimer_ss1_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss1_qmpphy_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
retimer_ss1_con_sbu_out: endpoint {
|
||||
remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c8 {
|
||||
@@ -634,6 +849,36 @@ &pcie6a_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550_gpios {
|
||||
rtmr0_default: rtmr0-reset-n-active-state {
|
||||
pins = "gpio10";
|
||||
function = "normal";
|
||||
power-source = <1>; /* 1.8V */
|
||||
};
|
||||
|
||||
rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {
|
||||
pins = "gpio11";
|
||||
function = "normal";
|
||||
power-source = <1>; /* 1.8V */
|
||||
};
|
||||
};
|
||||
|
||||
&pmc8380_5_gpios {
|
||||
rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {
|
||||
pins = "gpio8";
|
||||
function = "normal";
|
||||
power-source = <1>; /* 1.8V */
|
||||
};
|
||||
};
|
||||
|
||||
&pm8550ve_9_gpios {
|
||||
rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
|
||||
pins = "gpio8";
|
||||
function = "normal";
|
||||
power-source = <1>; /* 1.8V */
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -762,6 +1007,34 @@ wake-n-pins {
|
||||
};
|
||||
};
|
||||
|
||||
rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state {
|
||||
pins = "gpio188";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state {
|
||||
pins = "gpio175";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state {
|
||||
pins = "gpio186";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rtmr1_default: rtmr1-reset-n-active-state {
|
||||
pins = "gpio176";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tpad_default: tpad-default-state {
|
||||
disable-pins {
|
||||
pins = "gpio38";
|
||||
@@ -839,7 +1112,7 @@ &usb_1_ss0_dwc3_hs {
|
||||
};
|
||||
|
||||
&usb_1_ss0_qmpphy_out {
|
||||
remote-endpoint = <&pmic_glink_ss0_ss_in>;
|
||||
remote-endpoint = <&retimer_ss0_ss_in>;
|
||||
};
|
||||
|
||||
&usb_1_ss1_hsphy {
|
||||
@@ -871,5 +1144,5 @@ &usb_1_ss1_dwc3_hs {
|
||||
};
|
||||
|
||||
&usb_1_ss1_qmpphy_out {
|
||||
remote-endpoint = <&pmic_glink_ss1_ss_in>;
|
||||
remote-endpoint = <&retimer_ss1_ss_in>;
|
||||
};
|
||||
|
||||
@@ -743,7 +743,7 @@ gcc: clock-controller@100000 {
|
||||
|
||||
clocks = <&bi_tcxo_div2>,
|
||||
<&sleep_clk>,
|
||||
<0>,
|
||||
<&pcie3_phy>,
|
||||
<&pcie4_phy>,
|
||||
<&pcie5_phy>,
|
||||
<&pcie6a_phy>,
|
||||
@@ -2906,6 +2906,208 @@ mmss_noc: interconnect@1780000 {
|
||||
#interconnect-cells = <2>;
|
||||
};
|
||||
|
||||
pcie3: pcie@1bd0000 {
|
||||
device_type = "pci";
|
||||
compatible = "qcom,pcie-x1e80100";
|
||||
reg = <0x0 0x01bd0000 0x0 0x3000>,
|
||||
<0x0 0x78000000 0x0 0xf1d>,
|
||||
<0x0 0x78000f40 0x0 0xa8>,
|
||||
<0x0 0x78001000 0x0 0x1000>,
|
||||
<0x0 0x78100000 0x0 0x100000>,
|
||||
<0x0 0x01bd3000 0x0 0x1000>;
|
||||
reg-names = "parf",
|
||||
"dbi",
|
||||
"elbi",
|
||||
"atu",
|
||||
"config",
|
||||
"mhi";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>,
|
||||
<0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
dma-coherent;
|
||||
|
||||
linux,pci-domain = <3>;
|
||||
num-lanes = <8>;
|
||||
|
||||
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7",
|
||||
"global";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_3_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
|
||||
<&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"noc_aggr",
|
||||
"cnoc_sf_axi";
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "pcie-mem",
|
||||
"cpu-pcie";
|
||||
|
||||
resets = <&gcc GCC_PCIE_3_BCR>,
|
||||
<&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
|
||||
reset-names = "pci",
|
||||
"link_down";
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_3_GDSC>;
|
||||
|
||||
phys = <&pcie3_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
operating-points-v2 = <&pcie3_opp_table>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie3_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
/* GEN 1 x1 */
|
||||
opp-2500000 {
|
||||
opp-hz = /bits/ 64 <2500000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
opp-peak-kBps = <250000 1>;
|
||||
};
|
||||
|
||||
/* GEN 1 x2 and GEN 2 x1 */
|
||||
opp-5000000 {
|
||||
opp-hz = /bits/ 64 <5000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
opp-peak-kBps = <500000 1>;
|
||||
};
|
||||
|
||||
/* GEN 1 x4 and GEN 2 x2 */
|
||||
opp-10000000 {
|
||||
opp-hz = /bits/ 64 <10000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
opp-peak-kBps = <1000000 1>;
|
||||
};
|
||||
|
||||
/* GEN 1 x8 and GEN 2 x4 */
|
||||
opp-20000000 {
|
||||
opp-hz = /bits/ 64 <20000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
opp-peak-kBps = <2000000 1>;
|
||||
};
|
||||
|
||||
/* GEN 2 x8 */
|
||||
opp-40000000 {
|
||||
opp-hz = /bits/ 64 <40000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
opp-peak-kBps = <4000000 1>;
|
||||
};
|
||||
|
||||
/* GEN 3 x1 */
|
||||
opp-8000000 {
|
||||
opp-hz = /bits/ 64 <8000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
opp-peak-kBps = <984500 1>;
|
||||
};
|
||||
|
||||
/* GEN 3 x2 and GEN 4 x1 */
|
||||
opp-16000000 {
|
||||
opp-hz = /bits/ 64 <16000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
opp-peak-kBps = <1969000 1>;
|
||||
};
|
||||
|
||||
/* GEN 3 x4 and GEN 4 x2 */
|
||||
opp-32000000 {
|
||||
opp-hz = /bits/ 64 <32000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
opp-peak-kBps = <3938000 1>;
|
||||
};
|
||||
|
||||
/* GEN 3 x8 and GEN 4 x4 */
|
||||
opp-64000000 {
|
||||
opp-hz = /bits/ 64 <64000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
opp-peak-kBps = <7876000 1>;
|
||||
};
|
||||
|
||||
/* GEN 4 x8 */
|
||||
opp-128000000 {
|
||||
opp-hz = /bits/ 64 <128000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
opp-peak-kBps = <15753000 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie3_phy: phy@1be0000 {
|
||||
compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
|
||||
reg = <0 0x01be0000 0 0x10000>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
|
||||
<&tcsr TCSR_PCIE_8L_CLKREF_EN>,
|
||||
<&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
|
||||
<&gcc GCC_PCIE_3_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_3_PIPEDIV2_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg_ahb",
|
||||
"ref",
|
||||
"rchng",
|
||||
"pipe",
|
||||
"pipediv2";
|
||||
|
||||
resets = <&gcc GCC_PCIE_3_PHY_BCR>,
|
||||
<&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
|
||||
reset-names = "phy",
|
||||
"phy_nocsr";
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "pcie3_pipe_clk";
|
||||
|
||||
#phy-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie6a: pci@1bf8000 {
|
||||
device_type = "pci";
|
||||
compatible = "qcom,pcie-x1e80100";
|
||||
|
||||
Reference in New Issue
Block a user