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staging: vt6656: vnt_rf_write_embedded add reg length and IFREGCTL_REGW
The rf register always have *_REG_LEN and IFREGCTL_REGW macros added. *_REG_LEN is always 23(0x17) replace them with VNT_RF_REG_LEN. Remove *_REG_LEN and IFREGCTL_REGW from tables and vnt_rf_set_txpower and apply VNT_RF_REG_LEN and IFREGCTL_REGW in vnt_rf_write_embedded Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Malcolm Priestley
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
0e2b6fe1f4
commit
f1c840d55b
@@ -40,22 +40,18 @@
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#include "baseband.h"
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#include "usbpipe.h"
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#define BY_AL2230_REG_LEN 23 //24bit
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#define CB_AL2230_INIT_SEQ 15
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#define AL2230_PWR_IDX_LEN 64
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#define BY_AL7230_REG_LEN 23 //24bit
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#define CB_AL7230_INIT_SEQ 16
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#define AL7230_PWR_IDX_LEN 64
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//{{RobertYu:20051111
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#define BY_VT3226_REG_LEN 23
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#define CB_VT3226_INIT_SEQ 11
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#define VT3226_PWR_IDX_LEN 64
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//}}
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//{{RobertYu:20060609
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#define BY_VT3342_REG_LEN 23
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#define CB_VT3342_INIT_SEQ 13
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#define VT3342_PWR_IDX_LEN 64
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//}}
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@@ -390,20 +386,20 @@ static u8 vt3226_channel_table1[CB_MAX_CHANNEL_24G][3] = {
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};
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static const u32 vt3226d0_lo_current_table[CB_MAX_CHANNEL_24G] = {
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0x0135c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0135c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0235c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0235c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0235c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0335c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0335c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0335c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0335c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0335c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0335c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0335c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0335c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW,
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0x0135c600 + (BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW
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0x0135c600,
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0x0135c600,
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0x0235c600,
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0x0235c600,
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0x0235c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0135c600
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};
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static u8 vt3342a0_init_table[CB_VT3342_INIT_SEQ][3] = { /* 11b/g mode */
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@@ -547,70 +543,70 @@ static u8 vt3342_channel_table1[CB_MAX_CHANNEL][3] = {
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-*/
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static const u32 al2230_power_table[AL2230_PWR_IDX_LEN] = {
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0x04040900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04041900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04042900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04043900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04044900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04045900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04046900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04047900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04048900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04049900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0404a900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0404b900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0404c900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0404d900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0404e900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0404f900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04050900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04051900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04052900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04053900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04054900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04055900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04056900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04057900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04058900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04059900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0405a900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0405b900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0405c900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0405d900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0405e900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0405f900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04060900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04061900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04062900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04063900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04064900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04065900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04066900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04067900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04068900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04069900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0406a900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0406b900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0406c900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0406d900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0406e900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0406f900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04070900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04071900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04072900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04073900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04074900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04075900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04076900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04077900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04078900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x04079900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0407a900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0407b900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0407c900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0407d900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0407e900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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0x0407f900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW
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0x04040900,
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0x04041900,
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0x04042900,
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0x04043900,
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0x04044900,
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0x04045900,
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0x04046900,
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0x04047900,
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0x04048900,
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0x04049900,
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0x0404a900,
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0x0404b900,
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0x0404c900,
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0x0404d900,
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0x0404e900,
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0x0404f900,
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0x04050900,
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0x04051900,
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0x04052900,
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0x04053900,
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0x04054900,
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0x04055900,
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0x04056900,
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0x04057900,
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0x04058900,
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0x04059900,
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0x0405a900,
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0x0405b900,
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0x0405c900,
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0x0405d900,
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0x0405e900,
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0x0405f900,
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0x04060900,
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0x04061900,
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0x04062900,
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0x04063900,
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0x04064900,
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0x04065900,
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0x04066900,
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0x04067900,
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0x04068900,
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0x04069900,
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0x0406a900,
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0x0406b900,
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0x0406c900,
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0x0406d900,
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0x0406e900,
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0x0406f900,
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0x04070900,
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0x04071900,
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0x04072900,
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0x04073900,
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0x04074900,
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0x04075900,
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0x04076900,
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0x04077900,
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0x04078900,
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0x04079900,
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0x0407a900,
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0x0407b900,
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0x0407c900,
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0x0407d900,
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0x0407e900,
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0x0407f900
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};
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/*
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@@ -629,6 +625,8 @@ int vnt_rf_write_embedded(struct vnt_private *priv, u32 data)
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{
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u8 reg_data[4];
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data |= (VNT_RF_REG_LEN << 3) | IFREGCTL_REGW;
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reg_data[0] = (u8)data;
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reg_data[1] = (u8)(data >> 8);
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reg_data[2] = (u8)(data >> 16);
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@@ -752,11 +750,9 @@ int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate)
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ret &= vnt_rf_write_embedded(priv, al2230_power_table[power]);
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if (rate <= RATE_11M)
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ret &= vnt_rf_write_embedded(priv, 0x0001b400 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x0001b400);
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else
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ret &= vnt_rf_write_embedded(priv, 0x0005a400 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x0005a400);
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break;
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case RF_AL2230S:
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if (power >= AL2230_PWR_IDX_LEN)
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@@ -765,25 +761,19 @@ int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate)
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ret &= vnt_rf_write_embedded(priv, al2230_power_table[power]);
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if (rate <= RATE_11M) {
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ret &= vnt_rf_write_embedded(priv, 0x040c1400 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x00299b00 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x040c1400);
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ret &= vnt_rf_write_embedded(priv, 0x00299b00);
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} else {
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ret &= vnt_rf_write_embedded(priv, 0x0005a400 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x00099b00 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x0005a400);
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ret &= vnt_rf_write_embedded(priv, 0x00099b00);
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}
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break;
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case RF_AIROHA7230:
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if (rate <= RATE_11M)
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ret &= vnt_rf_write_embedded(priv, 0x111bb900 +
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(BY_AL7230_REG_LEN << 3)+IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x111bb900);
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else
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ret &= vnt_rf_write_embedded(priv, 0x221bb900 +
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(BY_AL7230_REG_LEN << 3)+IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x221bb900);
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if (power >= AL7230_PWR_IDX_LEN)
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return false;
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@@ -792,8 +782,7 @@ int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate)
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* 0x080F1B00 for 3 wire control TxGain(D10)
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* and 0x31 as TX Gain value
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*/
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power_setting = 0x080c0b00 | (power << 12) |
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(BY_AL7230_REG_LEN << 3) | IFREGCTL_REGW;
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power_setting = 0x080c0b00 | (power << 12);
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ret &= vnt_rf_write_embedded(priv, power_setting);
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@@ -802,8 +791,7 @@ int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate)
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case RF_VT3226:
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if (power >= VT3226_PWR_IDX_LEN)
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return false;
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power_setting = ((0x3f - power) << 20) | (0x17 << 8) |
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(BY_VT3226_REG_LEN << 3) | IFREGCTL_REGW;
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power_setting = ((0x3f - power) << 20) | (0x17 << 8);
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ret &= vnt_rf_write_embedded(priv, power_setting);
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@@ -815,13 +803,10 @@ int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate)
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if (rate <= RATE_11M) {
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u16 hw_value = priv->hw->conf.chandef.chan->hw_value;
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power_setting = ((0x3f - power) << 20) |
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(0xe07 << 8) | (BY_VT3226_REG_LEN << 3) |
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IFREGCTL_REGW;
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power_setting = ((0x3f - power) << 20) | (0xe07 << 8);
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ret &= vnt_rf_write_embedded(priv, power_setting);
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ret &= vnt_rf_write_embedded(priv, 0x03c6a200 +
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(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x03c6a200);
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dev_dbg(&priv->usb->dev,
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"%s 11b channel [%d]\n", __func__, hw_value);
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@@ -832,23 +817,17 @@ int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate)
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ret &= vnt_rf_write_embedded(priv,
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vt3226d0_lo_current_table[hw_value]);
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ret &= vnt_rf_write_embedded(priv, 0x015C0800 +
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(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x015C0800);
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} else {
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dev_dbg(&priv->usb->dev,
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"@@@@ vnt_rf_set_txpower> 11G mode\n");
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power_setting = ((0x3f - power) << 20) |
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(0x7 << 8) | (BY_VT3226_REG_LEN << 3) |
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IFREGCTL_REGW;
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power_setting = ((0x3f - power) << 20) | (0x7 << 8);
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ret &= vnt_rf_write_embedded(priv, power_setting);
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ret &= vnt_rf_write_embedded(priv, 0x00C6A200 +
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(BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x016BC600 +
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(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x00900800 +
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(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
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ret &= vnt_rf_write_embedded(priv, 0x00C6A200);
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ret &= vnt_rf_write_embedded(priv, 0x016BC600);
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ret &= vnt_rf_write_embedded(priv, 0x00900800);
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}
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break;
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@@ -856,9 +835,7 @@ int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate)
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if (power >= VT3342_PWR_IDX_LEN)
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return false;
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power_setting = ((0x3f - power) << 20) |
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(0x27 << 8) | (BY_VT3342_REG_LEN << 3) |
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IFREGCTL_REGW;
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power_setting = ((0x3f - power) << 20) | (0x27 << 8);
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ret &= vnt_rf_write_embedded(priv, power_setting);
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@@ -54,6 +54,7 @@
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#define RF_MASK 0x7F
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#define VNT_RF_MAX_POWER 0x3f
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#define VNT_RF_REG_LEN 0x17 /* 24 bit length */
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int vnt_rf_write_embedded(struct vnt_private *, u32);
|
||||
int vnt_rf_setpower(struct vnt_private *, u32, u32);
|
||||
|
||||
Reference in New Issue
Block a user