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drm/xe/mtl: Fix PAT table coherency settings

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Re-sync our MTL PAT table with the bspec.  1-way coherency should only
be set on table entry 3.  We do not want an incorrect setting here to
accidentally paper over other bugs elsewhere in the driver.

Bspec: 45101
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230324210415.2434992-6-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper
2023-03-24 14:04:14 -07:00
committed by Rodrigo Vivi
parent 366974e4a6
commit f16a3f6335
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/xe/xe_pat.c
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@@ -54,8 +54,8 @@ const u32 pvc_pat_table[] = {
const u32 mtl_pat_table[] = {
[0] = MTL_PAT_0_WB,
[1] = MTL_PAT_1_WT | MTL_2_COH_1W,
[2] = MTL_PAT_3_UC | MTL_2_COH_1W,
[1] = MTL_PAT_1_WT,
[2] = MTL_PAT_3_UC,
[3] = MTL_PAT_0_WB | MTL_2_COH_1W,
[4] = MTL_PAT_0_WB | MTL_3_COH_2W,
};