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drm/amd/display: Cleanup outdated interfaces in dcn401_clk_mgr
[WHY&HOW] - Remove legacy update clocks sequence - FCLK P-State allow message is not required Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone
committed by
Alex Deucher
Alex Deucher
parent
149bacfe9c
commit
f0aece43ee
@@ -628,207 +628,6 @@ static void dcn401_update_clocks_update_dentist(
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}
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static void dcn401_update_clocks_legacy(struct clk_mgr *clk_mgr_base,
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struct dc_state *context,
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bool safe_to_lower)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
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struct dc *dc = clk_mgr_base->ctx->dc;
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int display_count;
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bool update_dppclk = false;
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bool update_dispclk = false;
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bool enter_display_off = false;
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bool dpp_clock_lowered = false;
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struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
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bool force_reset = false;
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bool update_uclk = false, update_fclk = false;
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bool p_state_change_support;
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bool fclk_p_state_change_support;
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int total_plane_count;
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if (dc->work_arounds.skip_clock_update)
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return;
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if (clk_mgr_base->clks.dispclk_khz == 0 ||
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(dc->debug.force_clock_mode & 0x1)) {
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/* This is from resume or boot up, if forced_clock cfg option used,
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* we bypass program dispclk and DPPCLK, but need set them for S3.
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*/
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force_reset = true;
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dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
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/* Force_clock_mode 0x1: force reset the clock even it is the same clock
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* as long as it is in Passive level.
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*/
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}
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display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
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if (display_count == 0)
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enter_display_off = true;
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if (clk_mgr->smu_present) {
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if (enter_display_off == safe_to_lower)
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dcn401_smu_set_num_of_displays(clk_mgr, display_count);
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clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
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total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
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fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
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if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
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clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
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/* To enable FCLK P-state switching, send PSTATE_SUPPORTED message to PMFW */
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if (clk_mgr_base->clks.fclk_p_state_change_support) {
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/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
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dcn401_smu_send_fclk_pstate_message(clk_mgr, true);
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}
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}
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if (dc->debug.force_min_dcfclk_mhz > 0)
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new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
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new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
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if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
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clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
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if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DCFCLK))
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dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
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}
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if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
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clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
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if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DCFCLK))
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dcn401_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
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}
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if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
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/* We don't actually care about socclk, don't notify SMU of hard min */
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clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
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clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
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clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
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if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
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clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
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clk_mgr_base->clks.num_ways = new_clocks->num_ways;
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if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
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dcn401_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
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}
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p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
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if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.prev_p_state_change_support)) {
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clk_mgr_base->clks.p_state_change_support = p_state_change_support;
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clk_mgr_base->clks.fw_based_mclk_switching = p_state_change_support && new_clocks->fw_based_mclk_switching;
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/* to disable P-State switching, set UCLK min = max */
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if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
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dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
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clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
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}
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/* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
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if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
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update_fclk = true;
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}
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if (!clk_mgr_base->clks.fclk_p_state_change_support &&
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update_fclk &&
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dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_FCLK)) {
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/* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
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dcn401_smu_send_fclk_pstate_message(clk_mgr, false);
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}
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/* Always update saved value, even if new value not set due to P-State switching unsupported */
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if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
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clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
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update_uclk = true;
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}
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/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
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if (clk_mgr_base->clks.p_state_change_support &&
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(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) &&
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dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
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dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
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if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
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clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
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clk_mgr_base->clks.num_ways = new_clocks->num_ways;
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if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
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dcn401_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
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}
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}
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if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
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if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
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dpp_clock_lowered = true;
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clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
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clk_mgr_base->clks.actual_dppclk_khz = new_clocks->dppclk_khz;
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if (clk_mgr->smu_present && !dpp_clock_lowered && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DPPCLK))
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clk_mgr_base->clks.actual_dppclk_khz = dcn401_set_hard_min_by_freq_optimized(clk_mgr, PPCLK_DPPCLK, clk_mgr_base->clks.dppclk_khz);
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update_dppclk = true;
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}
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if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
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clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
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if (clk_mgr->smu_present && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK))
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clk_mgr_base->clks.actual_dispclk_khz = dcn401_set_hard_min_by_freq_optimized(clk_mgr, PPCLK_DISPCLK, clk_mgr_base->clks.dispclk_khz);
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update_dispclk = true;
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}
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if (!new_clocks->dtbclk_en && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {
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new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
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}
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/* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
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if (!dc->debug.disable_dtb_ref_clk_switch &&
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should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000) &&
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dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {
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/* DCCG requires KHz precision for DTBCLK */
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clk_mgr_base->clks.ref_dtbclk_khz =
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dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
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dcn401_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
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}
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if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
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if (dpp_clock_lowered) {
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/* if clock is being lowered, increase DTO before lowering refclk */
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dcn401_update_clocks_update_dpp_dto(clk_mgr, context,
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safe_to_lower, clk_mgr_base->clks.dppclk_khz);
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dcn401_update_clocks_update_dentist(clk_mgr, context);
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if (clk_mgr->smu_present && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DPPCLK)) {
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clk_mgr_base->clks.actual_dppclk_khz = dcn401_set_hard_min_by_freq_optimized(clk_mgr, PPCLK_DPPCLK,
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clk_mgr_base->clks.dppclk_khz);
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dcn401_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower,
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clk_mgr_base->clks.actual_dppclk_khz);
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}
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} else {
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/* if clock is being raised, increase refclk before lowering DTO */
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if (update_dppclk || update_dispclk)
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dcn401_update_clocks_update_dentist(clk_mgr, context);
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/* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
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* that we do not lower dto when it is not safe to lower. We do not need to
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* compare the current and new dppclk before calling this function.
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*/
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dcn401_update_clocks_update_dpp_dto(clk_mgr, context,
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safe_to_lower, clk_mgr_base->clks.actual_dppclk_khz);
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}
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}
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if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
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/*update dmcu for wait_loop count*/
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dmcu->funcs->set_psr_wait_loop(dmcu,
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clk_mgr_base->clks.dispclk_khz / 1000 / 7);
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}
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static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned int num_steps)
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{
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struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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@@ -1008,15 +807,15 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
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update_active_fclk = true;
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update_idle_fclk = true;
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/* To enable FCLK P-state switching, send PSTATE_SUPPORTED message to PMFW */
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if (clk_mgr_base->clks.fclk_p_state_change_support) {
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/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
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if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
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block_sequence[num_steps].params.update_pstate_support_params.support = true;
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block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
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num_steps++;
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}
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}
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/* To enable FCLK P-state switching, send PSTATE_SUPPORTED message to PMFW (message not supported on DCN401)*/
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// if (clk_mgr_base->clks.fclk_p_state_change_support) {
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// /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
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// if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
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// block_sequence[num_steps].params.update_pstate_support_params.support = true;
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// block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
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// num_steps++;
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// }
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// }
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}
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if (!clk_mgr_base->clks.fclk_p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
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@@ -1224,14 +1023,14 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
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// (*num_steps)++;
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// }
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/* disable FCLK P-State support if needed */
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if (!fclk_p_state_change_support &&
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should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_prev_p_state_change_support) &&
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dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
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block_sequence[num_steps].params.update_pstate_support_params.support = false;
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block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
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num_steps++;
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}
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/* disable FCLK P-State support if needed (message not supported on DCN401)*/
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// if (!fclk_p_state_change_support &&
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// should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_prev_p_state_change_support) &&
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// dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
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// block_sequence[num_steps].params.update_pstate_support_params.support = false;
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// block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
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// num_steps++;
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// }
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}
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if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching &&
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@@ -1412,11 +1211,6 @@ static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base,
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unsigned int num_steps = 0;
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if (dc->debug.enable_legacy_clock_update) {
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dcn401_update_clocks_legacy(clk_mgr_base, context, safe_to_lower);
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return;
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}
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/* build bandwidth related clocks update sequence */
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num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,
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context,
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@@ -1060,7 +1060,6 @@ struct dc_debug_options {
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uint32_t dml21_disable_pstate_method_mask;
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union fw_assisted_mclk_switch_version fams_version;
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union dmub_fams2_global_feature_config fams2_config;
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bool enable_legacy_clock_update;
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unsigned int force_cositing;
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unsigned int disable_spl;
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unsigned int force_easf;
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