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drm/i915: Apply the combo PLL frac w/a on DG1

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DG1 apparently needs the combo PLL fractional divider w/a
with 38.4 MHz refclk as well. This isn't listed in bspec, but
looking at the hsd it looks like it was possibly just missed
due to no one having a DG1 around at the time.

This gives us slightly more accurate clocks on DG1.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250401163752.6412-2-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
This commit is contained in:
Ville Syrjälä
2025-04-01 19:37:49 +03:00
parent d35b913f0e
commit efaa1177c3
1 changed files with 1 additions and 0 deletions
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1
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
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@@ -2604,6 +2604,7 @@ ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)
{
return ((display->platform.elkhartlake &&
IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||
display->platform.dg1 ||
display->platform.tigerlake ||
display->platform.alderlake_s ||
display->platform.alderlake_p) &&