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arm64: dts: qcom: sc8280xp: Add SDC2 and enable on CRD

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The CRD has Micro SD slot, introduce the necessary DeviceTree nodes for
enabling this.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517235217.1728548-1-quic_bjorande@quicinc.com
This commit is contained in:
Bjorn Andersson
2023-05-17 16:52:17 -07:00
committed by Bjorn Andersson
parent 42b0837549
commit ef026e592b
2 changed files with 124 additions and 0 deletions
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81
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
View File

@@ -308,6 +308,13 @@ vreg_l1c: ldo1 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c: ldo6 {
regulator-name = "vreg_l6c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c: ldo7 {
regulator-name = "vreg_l7c";
regulator-min-microvolt = <2504000>;
@@ -318,6 +325,13 @@ vreg_l7c: ldo7 {
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c: ldo9 {
regulator-name = "vreg_l9c";
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13c: ldo13 {
regulator-name = "vreg_l13c";
regulator-min-microvolt = <3072000>;
@@ -600,6 +614,19 @@ &remoteproc_nsp0 {
status = "okay";
};
&sdc2 {
pinctrl-0 = <&sdc2_default_state>;
pinctrl-1 = <&sdc2_sleep_state>;
pinctrl-names = "default", "sleep";
vmmc-supply = <&vreg_l9c>;
vqmmc-supply = <&vreg_l6c>;
cd-gpios = <&tlmm 131 GPIO_ACTIVE_LOW>;
status = "okay";
};
&uart17 {
compatible = "qcom,geni-debug-uart";
@@ -862,6 +889,60 @@ wake-n-pins {
};
};
sdc2_default_state: sdc2-default-state {
clk-pins {
pins = "sdc2_clk";
drive-strength = <16>;
bias-disable;
};
cmd-pins {
pins = "sdc2_cmd";
drive-strength = <16>;
bias-pull-up;
};
data-pins {
pins = "sdc2_data";
drive-strength = <16>;
bias-pull-up;
};
card-detect-pins {
pins = "gpio131";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
sdc2_sleep_state: sdc2-sleep-state {
clk-pins {
pins = "sdc2_clk";
drive-strength = <2>;
bias-disable;
};
cmd-pins {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-pull-up;
};
data-pins {
pins = "sdc2_data";
drive-strength = <2>;
bias-pull-up;
};
card-detect-pins {
pins = "gpio131";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
tpad_default: tpad-default-state {
int-n-pins {
pins = "gpio182";

43
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@@ -2845,6 +2845,49 @@ data-pins {
};
};
sdc2: mmc@8804000 {
compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
resets = <&gcc GCC_SDCC2_BCR>;
interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
iommus = <&apps_smmu 0x4e0 0x0>;
power-domains = <&rpmhpd SC8280XP_CX>;
operating-points-v2 = <&sdc2_opp_table>;
bus-width = <4>;
dma-coherent;
status = "disabled";
sdc2_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1800000 400000>;
opp-avg-kBps = <100000 0>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
opp-peak-kBps = <5400000 1600000>;
opp-avg-kBps = <200000 0>;
};
};
};
usb_0_qmpphy: phy@88eb000 {
compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
reg = <0 0x088eb000 0 0x4000>;