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drm/xe/oa: Refactor WAs to use XE_WA() macro

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Refactor Wa_18013179988, Wa_14015568240, Wa_1508761755, and
Wa_1509372804, to use the proper workaround-check implementation for
out-of-band workarounds, XE_WA(), and drop the use of the platform
based WA selection.

Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aradhya Bhatia <aradhya.bhatia@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250220094645.358647-3-aradhya.bhatia@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
This commit is contained in:
Aradhya Bhatia
2025-02-20 15:16:45 +05:30
committed by Lucas De Marchi
parent 8c5fe7d88b
commit eef3ede533
2 changed files with 14 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/gpu/drm/xe/xe_oa.c
View File

@@ -12,6 +12,8 @@
#include <drm/drm_managed.h>
#include <uapi/drm/xe_drm.h>
#include <generated/xe_wa_oob.h>
#include "abi/guc_actions_slpc_abi.h"
#include "instructions/xe_mi_commands.h"
#include "regs/xe_engine_regs.h"
@@ -35,6 +37,7 @@
#include "xe_sched_job.h"
#include "xe_sriov.h"
#include "xe_sync.h"
#include "xe_wa.h"
#define DEFAULT_POLL_FREQUENCY_HZ 200
#define DEFAULT_POLL_PERIOD_NS (NSEC_PER_SEC / DEFAULT_POLL_FREQUENCY_HZ)
@@ -812,11 +815,8 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
struct xe_mmio *mmio = &stream->gt->mmio;
u32 sqcnt1;
/*
* Wa_1508761755:xehpsdv, dg2
* Enable thread stall DOP gating and EU DOP gating.
*/
if (stream->oa->xe->info.platform == XE_DG2) {
/* Enable thread stall DOP gating and EU DOP gating. */
if (XE_WA(stream->gt, 1508761755)) {
xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN,
_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN2,
@@ -1065,11 +1065,10 @@ static int xe_oa_enable_metric_set(struct xe_oa_stream *stream)
int ret;
/*
* Wa_1508761755:xehpsdv, dg2
* EU NOA signals behave incorrectly if EU clock gating is enabled.
* Disable thread stall DOP gating and EU DOP gating.
*/
if (stream->oa->xe->info.platform == XE_DG2) {
if (XE_WA(stream->gt, 1508761755)) {
xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN,
_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN2,
@@ -1720,12 +1719,10 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
}
/*
* Wa_1509372804:pvc
*
* GuC reset of engines causes OA to lose configuration
* state. Prevent this by overriding GUCRC mode.
*/
if (stream->oa->xe->info.platform == XE_PVC) {
if (XE_WA(stream->gt, 1509372804)) {
ret = xe_guc_pc_override_gucrc_mode(&gt->uc.guc.pc,
SLPC_GUCRC_MODE_GUCRC_NO_RC6);
if (ret)
@@ -1857,23 +1854,14 @@ u32 xe_oa_timestamp_frequency(struct xe_gt *gt)
{
u32 reg, shift;
/*
* Wa_18013179988:dg2
* Wa_14015568240:pvc
* Wa_14015846243:mtl
*/
switch (gt_to_xe(gt)->info.platform) {
case XE_DG2:
case XE_PVC:
case XE_METEORLAKE:
if (XE_WA(gt, 18013179988) || XE_WA(gt, 14015568240)) {
xe_pm_runtime_get(gt_to_xe(gt));
reg = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);
xe_pm_runtime_put(gt_to_xe(gt));
shift = REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
return gt->info.reference_clock << (3 - shift);
default:
} else {
return gt->info.reference_clock;
}
}

5
drivers/gpu/drm/xe/xe_wa_oob.rules
View File

@@ -47,3 +47,8 @@ no_media_l3 MEDIA_VERSION(3000)
MEDIA_VERSION(1300)
14016712196 GRAPHICS_VERSION(1255)
GRAPHICS_VERSION_RANGE(1270, 1274)
14015568240 GRAPHICS_VERSION_RANGE(1255, 1260)
18013179988 GRAPHICS_VERSION(1255)
GRAPHICS_VERSION_RANGE(1270, 1274)
1508761755 GRAPHICS_VERSION(1255)
GRAPHICS_VERSION(1260), GRAPHICS_STEP(A0, B0)