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Merge series "Add Tegra Quad SPI driver" from Sowjanya Komatineni <skomatineni@nvidia.com>:
This series adds Tegra210, Tegra186, and Tegra194 Quad SPI driver and enables Quad SPI on Jetson Nano and Jetson Xavier NX. QSPI controller is available on Tegra210, Tegra186 and Tegra194. Tegra186 and Tegra194 has additional feature of combined sequence mode where command, address and data can all be transferred in a single transfer. Combined sequence mode is useful only when using DMA mode transfer. This series does not have combined sequence mode feature as Tegra186/Tegra194 GPCDMA driver is not upstreamed yet. This series includes - dt-binding document - QSPI driver for Tegra210/Tegra186/Tegra194 - Enables QSPI on Jetson Nano and Jetson Xavier NX. Delta between patch versions: [v5]: Simplified implementation in Patch-0006 [v4]: Updated dummy cycles implementation based on v3 feedback - Added dummy_data bit field int spi_transfer to indicate corresponding transfer is dummy bytes transfer. - Updated Tegra QSPI transfer_one_message to identify dummy transfer and to use HW supported dummy bytes transfer when dummy cycles are with in Tegra QSPI supported max HW dummy cycles otherwise fallsback to transfer dummy bytes from software. - Updated dt-bindings based on v3 feedback. [v3]: v2 has some mixed patches sent out accidentally. v3 sends proper patches with fixes mentioned in v2. [v2]: below v1 feedback - Added SPI_MASTER_USES_HW_DUMMY_CYCLES flag for controllers supporting hardware dummy cycles and skips dummy bytes transfer from software for these controllers. - Updated dt-binding doc with tx/rx tap delay properties. - Added qspi_out clock to dt-binding doc which will be used later with ddr mode support. - All other v1 feedback on some cleanup. Sowjanya Komatineni (9): dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM dt-bindings: spi: Add Tegra Quad SPI device tree binding MAINTAINERS: Add Tegra Quad SPI driver section spi: tegra210-quad: Add support for Tegra210 QSPI controller spi: spi-mem: Mark dummy transfers by setting dummy_data bit spi: tegra210-quad: Add support for hardware dummy cycles transfer arm64: tegra: Enable QSPI on Jetson Nano arm64: tegra: Add QSPI nodes on Tegra194 arm64: tegra: Enable QSPI on Jetson Xavier NX .../bindings/spi/nvidia,tegra210-quad.yaml | 117 ++ MAINTAINERS | 8 + .../dts/nvidia/tegra194-p3509-0000+p3668-0000.dts | 12 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 28 + arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 12 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-mem.c | 1 + drivers/spi/spi-tegra210-quad.c | 1410 ++++++++++++++++++++ include/dt-bindings/clock/tegra210-car.h | 2 +- include/linux/spi/spi.h | 2 + 12 files changed, 1604 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml create mode 100644 drivers/spi/spi-tegra210-quad.c -- 2.7.4
This commit is contained in:
Mark Brown
117
Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
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117
Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
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@@ -0,0 +1,117 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tegra Quad SPI Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jonathan Hunter <jonathanh@nvidia.com>
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allOf:
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- $ref: "spi-controller.yaml#"
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properties:
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compatible:
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enum:
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- nvidia,tegra210-qspi
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- nvidia,tegra186-qspi
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- nvidia,tegra194-qspi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clock-names:
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items:
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- const: qspi
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- const: qspi_out
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clocks:
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maxItems: 2
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resets:
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maxItems: 1
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: rx
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- const: tx
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patternProperties:
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"@[0-9a-f]+":
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type: object
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properties:
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spi-rx-bus-width:
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enum: [1, 2, 4]
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spi-tx-bus-width:
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enum: [1, 2, 4]
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nvidia,tx-clk-tap-delay:
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description:
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Delays the clock going out to device with this tap value.
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Tap value varies based on platform design trace lengths from Tegra
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QSPI to corresponding slave device.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 31
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nvidia,rx-clk-tap-delay:
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description:
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Delays the clock coming in from the device with this tap value.
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Tap value varies based on platform design trace lengths from Tegra
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QSPI to corresponding slave device.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 255
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required:
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- reg
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required:
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- compatible
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- reg
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- interrupts
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- clock-names
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- clocks
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- resets
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/reset/tegra210-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi@70410000 {
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compatible = "nvidia,tegra210-qspi";
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reg = <0x70410000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA210_CLK_QSPI>,
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<&tegra_car TEGRA210_CLK_QSPI_PM>;
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clock-names = "qspi", "qspi_out";
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resets = <&tegra_car 211>;
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dmas = <&apbdma 5>, <&apbdma 5>;
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dma-names = "rx", "tx";
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flash@0 {
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compatible = "spi-nor";
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reg = <0>;
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spi-max-frequency = <104000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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nvidia,tx-clk-tap-delay = <0>;
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nvidia,rx-clk-tap-delay = <0>;
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};
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};
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@@ -17498,6 +17498,14 @@ M: Laxman Dewangan <ldewangan@nvidia.com>
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S: Supported
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F: drivers/spi/spi-tegra*
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TEGRA QUAD SPI DRIVER
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M: Thierry Reding <thierry.reding@gmail.com>
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M: Jonathan Hunter <jonathanh@nvidia.com>
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M: Sowjanya Komatineni <skomatineni@nvidia.com>
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L: linux-tegra@vger.kernel.org
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S: Maintained
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F: drivers/spi/spi-tegra210-quad.c
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TEGRA VIDEO DRIVER
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M: Thierry Reding <thierry.reding@gmail.com>
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M: Jonathan Hunter <jonathanh@nvidia.com>
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@@ -843,6 +843,15 @@ config SPI_MXS
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help
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SPI driver for Freescale MXS devices.
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config SPI_TEGRA210_QUAD
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tristate "NVIDIA Tegra QSPI Controller"
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depends on ARCH_TEGRA || COMPILE_TEST
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depends on RESET_CONTROLLER
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help
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QSPI driver for NVIDIA Tegra QSPI Controller interface. This
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controller is different from the SPI controller and is available
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on Tegra SoCs starting from Tegra210.
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config SPI_TEGRA114
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tristate "NVIDIA Tegra114 SPI Controller"
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depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
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@@ -115,6 +115,7 @@ obj-$(CONFIG_SPI_ST_SSC4) += spi-st-ssc4.o
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obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
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obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
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obj-$(CONFIG_SPI_SYNQUACER) += spi-synquacer.o
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obj-$(CONFIG_SPI_TEGRA210_QUAD) += spi-tegra210-quad.o
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obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
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obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
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obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
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@@ -354,6 +354,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;
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xfers[xferpos].len = op->dummy.nbytes;
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xfers[xferpos].tx_nbits = op->dummy.buswidth;
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xfers[xferpos].dummy_data = 1;
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spi_message_add_tail(&xfers[xferpos], &msg);
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xferpos++;
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totalxferlen += op->dummy.nbytes;
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1410
drivers/spi/spi-tegra210-quad.c
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1410
drivers/spi/spi-tegra210-quad.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -307,7 +307,7 @@
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#define TEGRA210_CLK_AUDIO4 275
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#define TEGRA210_CLK_SPDIF 276
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/* 277 */
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/* 278 */
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#define TEGRA210_CLK_QSPI_PM 278
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/* 279 */
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/* 280 */
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#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
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@@ -825,6 +825,7 @@ extern void spi_res_release(struct spi_controller *ctlr,
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* transfer. If 0 the default (from @spi_device) is used.
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* @bits_per_word: select a bits_per_word other than the device default
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* for this transfer. If 0 the default (from @spi_device) is used.
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* @dummy_data: indicates transfer is dummy bytes transfer.
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* @cs_change: affects chipselect after this transfer completes
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* @cs_change_delay: delay between cs deassert and assert when
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* @cs_change is set and @spi_transfer is not the last in @spi_message
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@@ -937,6 +938,7 @@ struct spi_transfer {
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struct sg_table tx_sg;
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struct sg_table rx_sg;
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unsigned dummy_data:1;
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unsigned cs_change:1;
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unsigned tx_nbits:3;
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unsigned rx_nbits:3;
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