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serial: max310x: add comments for PLL limits

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Add comments to help clarify the provenance of the various hardcoded values
used in computing the ref clk.

Assisted-by: Gemini:Pro
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Link: https://patch.msgid.link/20260417-max310x-2-v1-10-b424e105ecac@dimonoff.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Hugo Villeneuve
2026-04-17 10:53:37 -04:00
committed by Greg Kroah-Hartman
parent 922cc077b2
commit ebd57bda9d
1 changed files with 17 additions and 0 deletions
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17
drivers/tty/serial/max310x.c
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@@ -585,6 +585,23 @@ static u8 max310x_pll_mult_to_id(u8 pll_mult)
}
}
/*
* From table 7 in datasheet: PLLFactor Selector Guide
*
* +-----------+----------------+-------------------+-------------------+
* | PLLFactor | MULTIPLICATION | fPLLIN | fREF |
* | (1 & 0) | FACTOR +---------+---------+---------+---------+
* | | | MIN | MAX | MIN | MAX |
* +-----------+----------------+---------+---------+---------+---------+
* | 0 | 6 | 500kHz | 800kHz | 3MHz | 4.8MHz |
* +-----------+----------------+---------+---------+---------+---------+
* | 1 | 48 | 850kHz | 1.2MHz | 40.8MHz | 56MHz |
* +-----------+----------------+---------+---------+---------+---------+
* | 2 | 96 | 425kHz | 1MHz | 40.8MHz | 96MHz |
* +-----------+----------------+---------+---------+---------+---------+
* | 3 | 144 | 390kHz | 667kHz | 56MHz | 96MHz |
* +-----------+----------------+---------+---------+---------+---------+
*/
static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
unsigned int freq, unsigned int *fref, bool xtal)
{