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drm/amd/display: Skip HDR metadata update when Smart Power OLED enabled

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[Why & How]
While smart power oled is enabled,
the infopacket contents are tied to the frame histogram,
so it does not need driver side to update the hdr metadata.

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ian Chen
2026-04-15 11:25:22 +08:00
committed by Alex Deucher
parent 35a8ecb704
commit ebb884dbb0
6 changed files with 18 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@@ -6533,6 +6533,10 @@ bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_
// send cmd
status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
// Update firmware_controlled_hdr_info_packet state on successful command execution
if (status && pipe_ctx)
pipe_ctx->stream->firmware_controlled_hdr_info_packet = enable;
return status;
}

1
drivers/gpu/drm/amd/display/dc/dc_stream.h
View File

@@ -304,6 +304,7 @@ struct dc_stream_state {
enum dc_drr_trigger_mode drr_trigger_mode;
struct dc_update_scratch_space *update_scratch;
bool firmware_controlled_hdr_info_packet;
};
#define ABM_LEVEL_IMMEDIATE_DISABLE 255

6
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
View File

@@ -470,7 +470,11 @@ void enc3_stream_encoder_update_dp_info_packets(
&info_frame->spd,
true);
}
if (info_frame->hdrsmd.valid) {
/* While smart power oled is enabled DMUB is scanning the contents of each frame
* and updating the HDR infopacket contents. Therefore we transition the infopacket
* programming control to DMUB while Smart Power OLED is enabled.
*/
if (info_frame->hdrsmd.valid && !info_frame->firmware_controlled_hdr_info_packet) {
enc->vpg->funcs->update_generic_info_packet(
enc->vpg,
3, /* packetIndex */

2
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
View File

@@ -468,7 +468,7 @@ static void dcn31_hpo_dp_stream_enc_update_dp_info_packets(
&info_frame->spd,
true);
if (info_frame->hdrsmd.valid)
if (info_frame->hdrsmd.valid && !info_frame->firmware_controlled_hdr_info_packet)
enc->vpg->funcs->update_generic_info_packet(
enc->vpg,
3, /* packetIndex */

6
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
View File

@@ -399,6 +399,9 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
pipe_ctx->stream_res.hpo_dp_stream_enc,
&pipe_ctx->stream_res.encoder_info_frame);
pipe_ctx->stream_res.encoder_info_frame.firmware_controlled_hdr_info_packet
= pipe_ctx->stream->firmware_controlled_hdr_info_packet;
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets(
pipe_ctx->stream_res.hpo_dp_stream_enc,
&pipe_ctx->stream_res.encoder_info_frame);
@@ -409,6 +412,9 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
pipe_ctx->stream_res.stream_enc,
&pipe_ctx->stream_res.encoder_info_frame);
pipe_ctx->stream_res.encoder_info_frame.firmware_controlled_hdr_info_packet
= pipe_ctx->stream->firmware_controlled_hdr_info_packet;
pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
pipe_ctx->stream_res.stream_enc,
&pipe_ctx->stream_res.encoder_info_frame);

1
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
View File

@@ -93,6 +93,7 @@ struct encoder_info_frame {
/* Adaptive Sync SDP*/
struct dc_info_packet adaptive_sync;
struct enc_sdp_line_num sdp_line_num;
bool firmware_controlled_hdr_info_packet;
};
struct encoder_unblank_param {