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drm/amd/display: log underflow

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as well as convert output in ref_cycle to nano sec

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Logatharshan Thothiralingam <Logatharshan.Thothiralingam@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tony Cheng
2017-08-03 09:22:14 -04:00
committed by Alex Deucher
parent 713950115b
commit eb4e33b7c9
3 changed files with 31 additions and 10 deletions
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33
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@@ -65,6 +65,20 @@ static void log_mpc_crc(struct core_dc *dc)
REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
}
void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
{
static const uint32_t ref_clk_mhz = 48;
static const unsigned int frac = 10;
uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
DTN_INFO("%d.%d \t ",
us_x10 / frac,
us_x10 % frac);
}
#define DTN_INFO_MICRO_SEC(ref_cycle) \
print_microsec(dc_ctx, ref_cycle)
static void dcn10_log_hw_state(struct core_dc *dc)
{
struct dc_context *dc_ctx = dc->ctx;
@@ -73,8 +87,9 @@ static void dcn10_log_hw_state(struct core_dc *dc)
DTN_INFO_BEGIN();
DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t rotation \t"
"mirror \t sw_mode \t dcc_en \t blank_en \t ttu_dis \t"
DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
"rotation \t mirror \t sw_mode \t "
"dcc_en \t blank_en \t ttu_dis \t underflow \t "
"min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
for (i = 0; i < pool->pipe_count; i++) {
@@ -83,9 +98,9 @@ static void dcn10_log_hw_state(struct core_dc *dc)
dcn10_mem_input_read_state(TO_DCN10_MEM_INPUT(mi), &s);
DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t %xh \t %xh \t "
"%d \t %d \t %d \t %d \t"
"%d \t %d \t %d \n",
DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
"%xh \t %xh \t %xh \t "
"%d \t %d \t %d \t %xh \t",
i,
s.pixel_format,
s.inuse_addr_hi,
@@ -97,9 +112,11 @@ static void dcn10_log_hw_state(struct core_dc *dc)
s.dcc_en,
s.blank_en,
s.ttu_disable,
s.min_ttu_vblank,
s.qos_level_low_wm,
s.qos_level_high_wm);
s.underflow_status);
DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
DTN_INFO("\n");
}
DTN_INFO("\n");

5
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
View File

@@ -841,9 +841,10 @@ void dcn10_mem_input_read_state(struct dcn10_mem_input *mi,
REG_GET(DCSURF_SURFACE_CONTROL,
PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
REG_GET_2(DCHUBP_CNTL,
REG_GET_3(DCHUBP_CNTL,
HUBP_BLANK_EN, &s->blank_en,
HUBP_TTU_DISABLE, &s->ttu_disable);
HUBP_TTU_DISABLE, &s->ttu_disable,
HUBP_UNDERFLOW_STATUS, &s->underflow_status);
REG_GET(DCN_GLOBAL_TTU_CNTL,
MIN_TTU_VBLANK, &s->min_ttu_vblank);

3
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
View File

@@ -250,6 +250,7 @@ struct dcn_mi_registers {
#define MI_MASK_SH_LIST_DCN(mask_sh)\
MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
MI_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
MI_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
@@ -402,6 +403,7 @@ struct dcn_mi_registers {
type HUBP_BLANK_EN;\
type HUBP_TTU_DISABLE;\
type HUBP_NO_OUTSTANDING_REQ;\
type HUBP_UNDERFLOW_STATUS;\
type NUM_PIPES;\
type NUM_BANKS;\
type PIPE_INTERLEAVE;\
@@ -591,6 +593,7 @@ struct dcn_hubp_state {
uint32_t sw_mode;
uint32_t dcc_en;
uint32_t blank_en;
uint32_t underflow_status;
uint32_t ttu_disable;
uint32_t min_ttu_vblank;
uint32_t qos_level_low_wm;